usbhost.c

RDC R2886 USB Ehci ohc测试源码,paradigm c++上运行测试

	//Set Command
	outport(0xFF08, PCIBase+DCR_Command);
	outport(0xFF0C, 0x0006);		//Enable PCI Master, Memory Access

   //set EHCI recommand value
   //set letency
   outport(0xFF08, PCIBase+0xC);
   outport(0xFF0C, 0x2000);
   //set Operation Mode Enable Reg
   outport(0xFF08, PCIBase+0x40);
   outport(0xFF0C, 0x0080);

	//Set OHCI Operational Memory Register -> 0x801000
	ohci_regs = (ohci_registers *)0x80100000L;

	//Set Base Address
	outport(0xFF08, OIPCIBase+DCR_BAL);
	outport(0xFF0C, 0x1000);
	outport(0xFF0E, 0x0080);

	//Set Command
	outport(0xFF08, OIPCIBase+DCR_Command);
	outport(0xFF0C, 0x0006);		//Enable PCI Master, Memory Access

   //set OHCI recommand value
   //set letency
   outport(0xFF08, OIPCIBase+0xC);
   outport(0xFF0C, 0x2008);
   //set Operation Mode Enable Reg
   outport(0xFF08, OIPCIBase+0x48);
   outport(0xFF0C, 0x027f);

	return TRUE;
}

void Init_USBHost_Info(void)
{
	int i;
	char __far *Host_memory_ptr;

	//OHCI
	//Allocate TD format structure
	Host_memory_ptr = (char *)malloc(sizeof(ohci_hcca_desc)+256);	//sizeof ohci_hcca_desc + 256
	Host_memory_ptr = (char *) (((unsigned long)Host_memory_ptr + 0xFF) & ~0xFF);

	ohci_hcca = (ohci_hcca_desc *) Host_memory_ptr;
	
	for(i=0;i<32;i++)
		ohci_hcca->int_table[i] = 1;
	ohci_hcca->frame_no = 0;
	ohci_hcca->pad1 = 0;
	ohci_hcca->done_head=0;

	//EHCI
	ehci_peri_frame_list = (u32 *)0x60000000L;

	//Allocate RDC UDISK descriptor and set value
	//Device descriptor
	Host_memory_ptr = (char *)malloc(sizeof(std_dev_des));
	UDisk_dev_des = (std_dev_des *) Host_memory_ptr;
	
	UDisk_dev_des->bLength = 0x12;
	UDisk_dev_des->bDescriptorType = 0x01;
	UDisk_dev_des->bcdUSB = 0x0200;
	UDisk_dev_des->bDeviceClass = 0x00;
	UDisk_dev_des->bDeviceSubClass = 0x00;
	UDisk_dev_des->bDeviceProtocal = 0x00;
	UDisk_dev_des->bMaxPacketSize = 0x40;
	UDisk_dev_des->idVendor = 0x0EA0;
	UDisk_dev_des->idProduct = 0x2168;
	UDisk_dev_des->bcdDevice = 0x0200;
	UDisk_dev_des->iManufacturer = 0x01;
	UDisk_dev_des->iProduct = 0x02;
	UDisk_dev_des->iSerialNumber = 0x03;
	UDisk_dev_des->bNumConfigurations = 0x01;
	
	//Configuration descriptor
	Host_memory_ptr = (char *)malloc(sizeof(std_cfg_des));
	UDisk_cfg_des = (std_cfg_des *) Host_memory_ptr;
	
	UDisk_cfg_des->bLength = 0x09;
	UDisk_cfg_des->bDescriptorType = 0x02;
	UDisk_cfg_des->wTotalLength = 0x0027;
	UDisk_cfg_des->bNumInterfaces = 0x01;
	UDisk_cfg_des->bConfigurationValue = 0x01;
	UDisk_cfg_des->iConfiguration = 0x00;
	UDisk_cfg_des->bmAttributes = 0x80;
	UDisk_cfg_des->MaxPower = 0x64;
	
	//Interface descriptor
	Host_memory_ptr = (char *)malloc(sizeof(std_if_des));
	UDisk_if_des = (std_if_des *) Host_memory_ptr;
	
	UDisk_if_des->bLength = 0x09;
	UDisk_if_des->bDescriptorType = 0x04;
	UDisk_if_des->bInterfaceNumber = 0x00;
	UDisk_if_des->bAlternateSetting = 0x00;
	UDisk_if_des->bNumEndpoints = 0x03;
	UDisk_if_des->bInterfaceClass = 0x08;
	UDisk_if_des->bInterfaceSubClass = 0x06;
	UDisk_if_des->bInterfaceProtocol = 0x50;
	UDisk_if_des->iInterface = 0x00;

	//Endpoint 1 descriptor
	Host_memory_ptr = (char *)malloc(sizeof(std_edp_des));
	UDisk_edp_des1 = (std_edp_des *) Host_memory_ptr;
	
	UDisk_edp_des1->bLength = 0x07;
	UDisk_edp_des1->bDescriptorType = 0x05;
	UDisk_edp_des1->bEndpointAddress = 0x81;
	UDisk_edp_des1->bmAttributes = 0x02;
	UDisk_edp_des1->wMaxPacketSize = 0x0200;
	UDisk_edp_des1->bInterval = 0x00;

	//Endpoint 2 descriptor
	Host_memory_ptr = (char *)malloc(sizeof(std_edp_des));
	UDisk_edp_des2 = (std_edp_des *) Host_memory_ptr;
	
	UDisk_edp_des2->bLength = 0x07;
	UDisk_edp_des2->bDescriptorType = 0x05;
	UDisk_edp_des2->bEndpointAddress = 0x02;
	UDisk_edp_des2->bmAttributes = 0x02;
	UDisk_edp_des2->wMaxPacketSize = 0x0200;
	UDisk_edp_des2->bInterval = 0x00;

	//Endpoint 3 descriptor
	Host_memory_ptr = (char *)malloc(sizeof(std_edp_des));
	UDisk_edp_des3 = (std_edp_des *) Host_memory_ptr;
	
	UDisk_edp_des3->bLength = 0x07;
	UDisk_edp_des3->bDescriptorType = 0x05;
	UDisk_edp_des3->bEndpointAddress = 0x83;
	UDisk_edp_des3->bmAttributes = 0x03;
	UDisk_edp_des3->wMaxPacketSize = 0x0002;
	UDisk_edp_des3->bInterval = 0x01;
	
	//LANGID
	UDisk_LANGID[0] = 0x04;
	UDisk_LANGID[1] = 0x03;
	UDisk_LANGID[2] = 0x09;
	UDisk_LANGID[3] = 0x04;
	
	//String 2
	Host_memory_ptr = UDisk_String2;
	*Host_memory_ptr++ = 0x22;
	*Host_memory_ptr++ = 0x03;
	*Host_memory_ptr++ = 0x46;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x6C;
	
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x61;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x73;
	*Host_memory_ptr++ = 0x00;
	
	*Host_memory_ptr++ = 0x68;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x20;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x44;
	
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x69;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x73;
	*Host_memory_ptr++ = 0x00;
	
	*Host_memory_ptr++ = 0x6B;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x20;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x20;
	
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x20;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x20;
	*Host_memory_ptr++ = 0x00;
	
	*Host_memory_ptr++ = 0x20;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x20;
	*Host_memory_ptr++ = 0x00;
	
	//String 2
	Host_memory_ptr = UDisk_String3;
	*Host_memory_ptr++ = 0x22;
	*Host_memory_ptr++ = 0x03;
	*Host_memory_ptr++ = 0x33;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x45;	
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x45;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x38;
	*Host_memory_ptr++ = 0x00;	
	*Host_memory_ptr++ = 0x39;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x34;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x34;	
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x39;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x33;
	*Host_memory_ptr++ = 0x00;	
	*Host_memory_ptr++ = 0x46;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x32;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x30;	
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x32;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x35;
	*Host_memory_ptr++ = 0x00;	
	*Host_memory_ptr++ = 0x30;
	*Host_memory_ptr++ = 0x00;
	*Host_memory_ptr++ = 0x43;
	*Host_memory_ptr++ = 0x00;
	
	//Allocate device descriptor +++++++++++++++++++++
	//Device descriptor
	Host_memory_ptr = (char *)malloc(sizeof(std_dev_des));
	dev_des = (std_dev_des *) Host_memory_ptr;
	for(i=0;i<sizeof(std_dev_des);i++)
		*Host_memory_ptr++ = 0;

	//Configuration descriptor
	Host_memory_ptr = (char *)malloc(sizeof(std_cfg_des)+sizeof(std_if_des)
		+sizeof(std_edp_des)+sizeof(std_edp_des)+sizeof(std_edp_des)+sizeof(std_edp_des));
	cfg_des = (std_cfg_des *) Host_memory_ptr;
	for(i=0;i<sizeof(std_cfg_des);i++)
		*Host_memory_ptr++ = 0;

	//Interface descriptor
	if_des = (std_if_des *) Host_memory_ptr;
	for(i=0;i<sizeof(std_if_des);i++)
		*Host_memory_ptr++ = 0;

	//Endpoint 1 descriptor
	edp_des1 = (std_edp_des *) Host_memory_ptr;
	for(i=0;i<sizeof(std_edp_des);i++)
		*Host_memory_ptr++ = 0;

	//Endpoint 2 descriptor
	edp_des2 = (std_edp_des *) Host_memory_ptr;
	for(i=0;i<sizeof(std_edp_des);i++)
		*Host_memory_ptr++ = 0;

	//Endpoint 3 descriptor
	edp_des3 = (std_edp_des *) Host_memory_ptr;
	for(i=0;i<sizeof(std_edp_des);i++)
		*Host_memory_ptr++ = 0;

	//Endpoint 4 descriptor
	edp_des4 = (std_edp_des *) Host_memory_ptr;
	for(i=0;i<sizeof(std_edp_des);i++)
		*Host_memory_ptr++ = 0;

	Test_Mode_operate();
}

void Init_ControlDescriptor(void)
{
    int i;
    char *p;

    p=(char*)dev_des;
    for(i=0;i<sizeof(std_dev_des);i++)
    	*p++=0;

    p=(char*)cfg_des;
    for(i=0;i<sizeof(std_cfg_des);i++)
    	*p++=0;

    p=(char*)if_des;
    for(i=0;i<sizeof(std_if_des);i++)
    	*p++=0;

    p=(char*)edp_des1;
    for(i=0;i<sizeof(std_edp_des);i++)
    	*p++=0;

    p=(char*)edp_des2;
    for(i=0;i<sizeof(std_edp_des);i++)
    	*p++=0;

    p=(char*)edp_des3;
    for(i=0;i<sizeof(std_edp_des);i++)
    	*p++=0;

    for(i=0;i<sizeof(String1);i++)
    {
        String1[i]=0;
        String2[i]=0;
        String3[i]=0;
    }

    for(i=0;i<sizeof(LANGID);i++)
    {
        LANGID[i]=0;
    }
}

BOOL Init_USB(void)
{
	int i;
	u32 __far *p;
	u32 fminterval;

	//EHCI
	//Reset EHCI Host Control
	DWordWrite(&ehci_regs->command, CMD_RESET);
	do{} while((DWordRead(&ehci_regs->command) & CMD_RESET) == CMD_RESET);
	
	
	if(ehci_caps->length != 0x0020)	//Read CapLength
		return FALSE;

	if((PCIBase & 0x0300) == 0x0300)	//ALI usb
	{
		if(ehci_caps->hci_version != 0x100)
			return FALSE;
		if(ehci_caps->hcs_params != 0x00101216L)
			return FALSE;
		if(ehci_caps->hcc_params != 0x7002)
			return FALSE;
	}
	else					//SIS
	{
		if(ehci_caps->hci_version != 0x0100)
			return FALSE;
		if(ehci_caps->hcs_params != 0x00101202L)
			return FALSE;
		if(ehci_caps->hcc_params != 0x7070)
			return FALSE;
	}		

	/* Tell the controller where the control and bulk lists are
	 * The lists are empty now. */
	DWordWrite(&ehci_regs->segment, 0x00000000);
	
	/* Choose the interrupts we care about now, others later on demand */
	DWordWrite(&ehci_regs->intr_enable, 0x37);

	DWordWriteHL(&ehci_regs->frame_list, UpperAddr(ehci_peri_frame_list), LowerAddr(ehci_peri_frame_list));
	p=ehci_peri_frame_list;
	for(i=0;i<1024;i++)
		*p++ = 1;
	 
	DWordWrite(&ehci_regs->frame_index, 0x00000000);
	DWordWrite(&ehci_regs->async_next, 0x00000000);

	DWordWrite(&ehci_regs->command, (0x00080000L | CMD_RUN));  	

	DWordWrite(&ehci_regs->configured_flag, FLAG_CF);

	DWordWrite(&ehci_regs->port_status[USB_Port], PORT_POWER);
	DWordWrite(&ehci_regs->port_status[USB_Port], EHCI_PORT_INIT);
	
	mdelay (0x200);
	
	//OHCI
	if(DWordRead(&ohci_regs->revision) != 0x00000110)	//Read HcRevision
		return FALSE;
	
	/* Tell the controller where the control and bulk lists are
	 * The lists are empty now. */
	DWordWrite(&ohci_regs->ed_controlhead, 0x00000000);
	DWordWrite(&ohci_regs->ed_bulkhead, 0x00000000);

	DWordWriteHL(&ohci_regs->hcca, UpperAddr(ohci_hcca), LowerAddr(ohci_hcca));

  	fminterval = 0x2edf;
	DWordWrite(&ohci_regs->periodicstart, (fminterval * 9) / 10);
   //DWordWrite(&ohci_regs->periodicstart, 0x3e67);
	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
	DWordWrite(&ohci_regs->fminterval, fminterval);
	DWordWrite(&ohci_regs->lsthresh, 0x00000628);

 	/* start controller operations */
 	DWordWrite(&ohci_regs->control, (OHCI_CONTROL_INIT | OHCI_USB_OPER));
 
	/* Choose the interrupts we care about now, others later on demand */
	DWordWrite(&ohci_regs->intrenable
		,( OHCI_INTR_MIE | OHCI_INTR_OC | OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_RD | OHCI_INTR_WDH | OHCI_INTR_SO));
	DWordWrite(&ohci_regs->intrstatus
		,( OHCI_INTR_MIE | OHCI_INTR_OC | OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_RD | OHCI_INTR_WDH | OHCI_INTR_SO));

	DWordWrite (&ohci_regs->a, 0x02000000L | ((RH_A_NPS | RH_A_NDP) & ~RH_A_PSM));
	DWordWrite (&ohci_regs->status, RH_HS_LPSC);

	mdelay (0x200);

	return TRUE;
}
//INTC for OHCI
void _interrupt OHCI_Isr()
{
 	u32 ints, rhs, rhpt1s;
 	static char buf[32];

 	char buf3[28]={"Full Speed device attach..."};
 	char buf4[28]={"Full Speed device detach..."};
   char buf5[28]={"Low Speed device attach..."};
 	char buf6[28]={"Low Speed device detach..."};
 	char *p, *q;
 	int i;

   INTA_Cnt++;

	ints=inport(INT_INSERV);    //read in-service register
	
	//Check Interrupt Status
	ints = DWordRead(&ohci_regs->intrstatus);

   if (ints == ~(u32)0)
		goto Exit_INTB_ISR;

	if (ints & OHCI_INTR_UE) {
	//In application, need to modify the unrecoverable Error
	}

	//Write back DoneHead
	if (ints & OHCI_INTR_WDH) {
      asm{pushf};	// 12/09/2003 Sten, for data consistent
   	asm{cli};
		DH_Status = dl_done_list();
      asm{popf};