usbhost.c

RDC R2886 USB Ehci ohc测试源码,paradigm c++上运行测试

// USB Host Controller test pattern Main file
// 05/19/2003    Jeff

#include <systypes.h>					/* Paradigm C++ standard types */
#include <stdio.h>
#include <dos.h>
#include <alloc.h>
#include <embedded.h>
#include <string.h>
#include <conio.h>
#include "..\Include\USBHost.h"
#include "..\Include\USBOHCI.h"
#include "..\Include\PCI.h"

#define EHCI_PORT_INIT	(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E|PORT_POWER)
/* For initializing controller (mask in an HCFS mode too) */
#define	OHCI_CONTROL_INIT \
	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | OHCI_CTRL_CLE | OHCI_CTRL_BLE


/* +++++++++++++++++++++ USBHost.c ++++++++++++++++++++++++ */
void Init_USBHost_system(void);
BOOL Init_PCI(void);
BOOL Init_USB(void);
void Init_USBHost_Info(void);
void _interrupt UsbIsr();
void _interrupt OHCI_Isr();
void _interrupt UartIsr();

void Init_PCINic(DEC_STRU far *);
uint32 linear_to_real(uint32);
void init_dec_desc(DEC_STRU far *, DEC_DESCRIPTOR far *, char far *);
void DEC_Regs_Init(DEC_STRU far *);
uint32 InPortD(uint16);
void OutPortD(uint16, uint32);
void pci_tx_handler(DEC_STRU far *);
void pci_rx_handler(DEC_STRU far *);

/* +++++++++++++++++++++ USBLib.c +++++++++++++++++++++++++ */
unsigned int UpperAddr (void far *p);
unsigned int LowerAddr (void far *p);
void DWordWrite(void far *p, u32 data);
void DWordWriteHL(void far *p, u16 dataH, u16 dataL);
u32 DWordRead(void far *p);
void mdelay(u16 ms);

/* +++++++++++++++++++++ USBHCD.c +++++++++++++++++++++++++ */
BOOL DoTest_Mode(int num);
BOOL EndTest_Mode(void);
BOOL InitEDTD(void);
BOOL InitControlTransfer(void);
BOOL DoControlTransfer(void);
void SendDesc2UART(void);

/* +++++++++++++++++++++ SCSIBLK.c +++++++++++++++++++++++++ */
void Init_scsiblk(void);
BOOL AllocateDisk(void);
void SendSCSI2UART(void);

/* +++++++++++++++++++++ USBUART.c +++++++++++++++++++++++++ */
void Test_Mode_operate(void);
void UART_SendData(char* buf, int size);

//OHCI
/* +++++++++++++++++++++ OHCIHCD.c +++++++++++++++++++++++++ */
BOOL InitOHCIControlTransfer(void);
BOOL dl_done_list(void);
BOOL DoOHCIControlTransfer(void);
BOOL OHCI_InitEDTD(void);

/* +++++++++++++++++++++ OHCISCSIBLK.c +++++++++++++++++++++++++ */
void OHCI_Init_scsiblk(void);
BOOL OHCI_AllocateDisk(void);

/* +++++++++++++++++++++ Global Variable +++++++++++++++++++++++++ */
// PCI NIC
DEC_STRU __far dec_info;

//EHCI
u16	PCIBase;
ehci_capability __far *ehci_caps;
ehci_registers __far *ehci_regs;

u32 __far *ehci_peri_frame_list;
ehci_qh __far *ehci_Ep0;
ehci_qtd __far *ehci_Ctl_TD1;
ehci_qtd __far *ehci_Ctl_TD2;
ehci_qtd __far *ehci_Ctl_TD3;

setup_format __far *Ctl_Setup;
char __far *Ctl_Data;

std_dev_des __far *dev_des;
std_cfg_des __far *cfg_des;
std_if_des  __far *if_des;
std_edp_des __far *edp_des1;
std_edp_des __far *edp_des2;
std_edp_des __far *edp_des3;
std_edp_des __far *edp_des4;
char LANGID[4];
char String2[256];
char String3[256];

std_dev_des __far *UDisk_dev_des;
std_cfg_des __far *UDisk_cfg_des;
std_if_des  __far *UDisk_if_des;
std_edp_des __far *UDisk_edp_des1;
std_edp_des __far *UDisk_edp_des2;
std_edp_des __far *UDisk_edp_des3;
char UDisk_LANGID[4];
char UDisk_String2[34];
char UDisk_String3[34];

//OHCI
u16	OIPCIBase;
ohci_registers __far *ohci_regs;
ohci_hcca_desc __far *ohci_hcca;
ohci_ed_t __far *ohci_Ep0;
ohci_td_t __far *ohci_Ctl_TD0;
ohci_td_t __far *ohci_Ctl_TD1;
ohci_td_t __far *ohci_Ctl_TD2;
ohci_td_t __far *ohci_Ctl_TD3;

//Others
int Do_TD_Complete;
int ErrorCnt;
BOOL DoneHeadClear;
u8 g_PortAttach;

u8 g_OHCIAttach;
BOOL DH_Status;
u16 TD_Status;
BOOL OHCI_DeviceAttach_Init;

BOOL DeviceAttach_Init;

BOOL HighSpeed_Owner;

BOOL ControlStart;
int ControlCnt;

BOOL SCSIStart;
int SCSICnt;

int UartCnt;
static char UartBuf[20];
BOOL BulkLoopInitData;

void main(void)
{
	u32 ints;//, rhs, rhpt1s, rhpt2s;

	asm {cli};
	Init_USBHost_system();
	if(Init_PCI() == FALSE)
		goto ErrorEND;

	Init_PCINic((DEC_STRU far *)&dec_info);
	Init_USBHost_Info();
	if(Init_USB() == FALSE)
		goto ErrorEND;

	/* Enable INTA and low level trigger mode */		
   	outport(0xFF48, 0x0030);	//INTA Level, low, priority = 0
   	outport(0xFF4A, 0x0030);	//INTB Level, low, priority = 0
   	outport(0xFF42, 0x0017);	//Level, low, priority = 0
   	outport(0xFF28, 0x05FD);	//Enable INTA, INTB, uart1

	asm{sti};

	if(InitEDTD() == FALSE)
		goto ErrorEND;
	if(OHCI_InitEDTD() == FALSE)
		goto ErrorEND;
	Init_scsiblk();
	OHCI_Init_scsiblk();

	while(1)
	{
		if(ControlStart == TRUE){
			outport(0xFF42, 0x001f);	//mask UART1 interrupt
			if(HighSpeed_Owner == TRUE){
				//EHCI
				if(DeviceAttach_Init == FALSE){
					do{} while(g_PortAttach == 0);
					if(InitControlTransfer() == FALSE)
						goto ErrorEND;
					DeviceAttach_Init = TRUE;
				}
				else{
					if(DoControlTransfer() == FALSE)
						goto ErrorEND;
				}
			}
			else{
				//OHCI
				if(OHCI_DeviceAttach_Init == FALSE){
					do{} while(g_OHCIAttach == 0);
					if(InitOHCIControlTransfer() == FALSE)
						goto ErrorEND;
					OHCI_DeviceAttach_Init = TRUE;
				}
				else{
					if(DoOHCIControlTransfer() == FALSE)
						goto ErrorEND;
				}
			}
			outport(0xFF42, 0x0017);	//enable UART1 interrupt
		}
		if(SCSIStart == TRUE){
			outport(0xFF42, 0x001f);	//mask UART1 interrupt
			if(HighSpeed_Owner == TRUE){
				//EHCI
				if(AllocateDisk() == FALSE)
					goto ErrorEND;

			}
			else{
				//OHCI
				if(OHCI_AllocateDisk() == FALSE)
					goto ErrorEND;
			}
			outport(0xFF42, 0x0017);	//enable UART1 interrupt
		}

		ErrorCnt = ErrorCnt;
		ints = ehci_regs->status;
		if(ErrorCnt != 0)
			goto ErrorEND;

		if(DH_Status == FALSE)
			goto ErrorEND;
	}

ErrorEND:
	while(1)
	{
		ErrorCnt = ErrorCnt;
		ints = ehci_regs->status;
		ints = ints;
	}
}

void Init_USBHost_system(void)
{
   	outport(0xffa0, UCS_CONTROL);		/* UCS */
   	outport(0xffa2, LCS_CONTROL);		/* LCS */
   	outport(0xffaa, MUL_CONTROL);		/* LCS/UCS/PCS multiple register */
//   	outport(0xffa8, 0x8002);		/* PCS & MCS auxiliary */
   	outport(0xffa4, 0x000f);		/* 08/06 Sten */
 	outport(0xfef0, ARBITER_CONTROL);	/* SDRAM arbiter control register */
 	outport(0xfef2, SDRAM_MODE_SET);		/* SDRAM mode setting */
 	outport(0xfef4, SDRAM_CTRL);		/* SDRAM control register */
 	outport(0xfef6, SDRAM_TIMING);		/* SDRAM timing register */
 	outport(0xffe2, REFRESH_COUNT);		/* Clock pre-scaler for re-fresh */
 	outport(0xffe4, 0x8000);		/* Enable RCU Register */
 	outport(0xffe6, 0x3333);		/* Watch-dog Timer write sequence */
 	outport(0xffe6, 0xcccc);		/* Watch-dog Timer write sequence */
 	outport(0xffe6, 0x0000);		/* Disable Watch-dog timer */

 	/* PIO mode */
 	outport(0xff6A, 0x0000);
 	outport(0xff76, PIO_MODE1_SET);
 	outport(0xff70, 0x0000);
 	/* PIO direction */
 	outport(0xff6C, 0x0000);
 	outport(0xff78, 0x0000);		/* PIO 27,28,29,30 input */
 	outport(0xff72, 0x0000);

	/* LED Port */
	outport(PIO_DATA1_REG, PIO_MODE1_SET);
	
   	/* Register Interrupt A handler */
   	setvect(INTA_TYPE, UsbIsr);
   	setvect(INTB_TYPE, OHCI_Isr);
   	setvect(UART1_TYPE, UartIsr);

	//Set UART1 115200, no parity, 1 stop bit
	outport(PCBBase+LCR, DLABH);
	outport(PCBBase+DLL, BAUDDIVL);
	outport(PCBBase+DLM, BAUDDIVH);
	
	//Trans DMA0, Tx & Rx FIFO reset, FIFO enable
	outport(PCBBase+FCR, 0x60F);
	mdelay(1);
	
	//Parity enable, 8-bit character
	outport(PCBBase+LCR, 0x04|bitlen);
	
	outport(PCBBase+IER, 0x01);	//enable receive data ready
   	
   	ErrorCnt = 0;
   	DoneHeadClear = FALSE;
   	DH_Status = TRUE;
   	TD_Status = 0;
   	g_PortAttach = 0;
   	g_OHCIAttach = 0;

	UartCnt = 0;
	ControlStart = FALSE;
	SCSIStart = FALSE;
	DeviceAttach_Init = FALSE;
	OHCI_DeviceAttach_Init = FALSE;
	HighSpeed_Owner = TRUE;
	BulkLoopInitData = FALSE;
}

BOOL Init_PCI(void)
{
	u16 Temp, Temp1;
	
	// Initial Bus to Normal Bus
	outport(0xFFEA, 0x8000);

	//Initial the Bridge and Device
	outport(0xFF0A, 0x8000);		// Bus 0, CFG Access Enable

	//Write PCI Bridge Memory Space Base Address Mask
	outport(0xFF08, B_MemBasAddrMask);	//Dev 0, Fun 0, Reg 40h
	outport(0xFF0E, 0x00FF);
	outport(0xFF0C, 0xE000);		//Mask 4k bytes

	//Write PCI Bridge Memory Space Base Address
	outport(0xFF08, B_MemBasAddr);		//Dev 0, Fun 0, Reg 44h
	outport(0xFF0E, 0x0080);		//Hword write first
	outport(0xFF0C, 0x0001);		//Base 800000, IE 1

	//Write PCI Bridge IO Base Address Mask
	outport(0xFF08, B_IOBasAddrMask);	//Dev 0, Fun 0, Reg 4Ch
	outport(0xFF0E, 0x00FF);
	outport(0xFF0C, 0xFF00);		//Mask 256 bytes

	//Write PCI Bridge IO Base Address
	outport(0xFF08, B_IOBasAddr);		//Dev 0, Fun 0, Reg 48h
	outport(0xFF0E, 0x0000);		//Hword write first
	outport(0xFF0C, PCI_IO_START | 1);		//Base 6000, IE 1

	//Search PCI Device: ALI/SIS USB Host, Fun 1 -> EHCI, Fun 0 -> OHCI
	//Check OHCI first, Function 0
	OIPCIBase = 0x0800;

Search_Oth_Dev:
	outport(0xFF08, OIPCIBase);		//Dev 1, Fun 0, Reg 0
	Temp = inport(0xFF0C);
	Temp1 = inport(0xFF0E);
	if((Temp != 0x1039) || (Temp1 != 0x7001))
	{
		if((Temp != 0x10B9) || (Temp1 != 0x5237))
		{
			PCIBase += 0x0800;
			OIPCIBase += 0x0800;
			goto Search_Oth_Dev;
		}
		else
			PCIBase = OIPCIBase | 0x0300;	//Ali Fun 3
	}
	else
		PCIBase = OIPCIBase | 0x0100;	//SIS Fun 1

	//Check EHCI
	if((PCIBase & 0x0300) == 0x0300)	//ALI usb
	{
		outport(0xFF08, PCIBase);		//Dev 1, Fun 3, Reg 0
		Temp = inport(0xFF0C);
		Temp1 = inport(0xFF0E);
		if((Temp != 0x10B9) || (Temp1 != 0x5239))
			return FALSE;
	}
	else					//SIS usb
	{
		outport(0xFF08, PCIBase);		//Dev 1, Fun 1, Reg 0
		Temp = inport(0xFF0C);
		Temp1 = inport(0xFF0E);
		if((Temp != 0x1039) || (Temp1 != 0x7002))
			return FALSE;
	}

	//Set EHCI Operational Memory Register -> 0x800000
	ehci_caps = (ehci_capability *)0x80000000L;
	ehci_regs = (ehci_registers *)0x80000020L;

	//Set Base Address
	outport(0xFF08, PCIBase+DCR_BAL);
	outport(0xFF0C, 0x0000);
	outport(0xFF0E, 0x0080);

	//Set Command
	outport(0xFF08, PCIBase+DCR_Command);
	outport(0xFF0C, 0x0006);		//Enable PCI Master, Memory Access

	//Set OHCI Operational Memory Register -> 0x801000
	ohci_regs = (ohci_registers *)0x80100000L;

	//Set Base Address
	outport(0xFF08, OIPCIBase+DCR_BAL);
	outport(0xFF0C, 0x1000);
	outport(0xFF0E, 0x0080);

	//Set Command
	outport(0xFF08, OIPCIBase+DCR_Command);
	outport(0xFF0C, 0x0006);		//Enable PCI Master, Memory Access

   // Search Davicom NIC
   outport(0xFF08, 0x1000);		//Dev 2, Fun 0, Reg 0
	Temp = inport(0xFF0C);
	Temp1 = inport(0xFF0E);
   if ((Temp!= DM9102_VID) || (Temp1 != DM9102_DID))
   	return FALSE;

	// Init Davicom NIC
	dec_info.handle = 0x1000;
   dec_info.io_base = PCI_NIC0_IO;
   dec_info.irq = 0x1000;		/* PCI INTB */
   dec_info.ctype = 0x2;
   dec_info.cr0_datal = 0;
   dec_info.cr0_datah = 0;
   dec_info.cr6_datal = (0x00212442L & (~ 0x0C00));
   dec_info.cr6_datah = 0x00212442L >> 16;
   dec_info.TxFreeDesc = DESC_COUNT;
   dec_info.RxFreeDesc = DESC_COUNT;

	outport(0xFF08, 0x1010);		// IO Base
   outport(0xFF0C, PCI_NIC0_IO);	// 0x6000
   outport(0xFF0E, 0x0000);

	outport(0xFF08, 0x1004);	//Command & Status
   outport(0xFF0C, 0x0005);	// Master & I/O

	return TRUE;
}

void Init_USBHost_Info(void)
{
	int i;
	char __far *Host_memory_ptr;

	//OHCI
	//Allocate TD format structure
	Host_memory_ptr = (char *)malloc(sizeof(ohci_hcca_desc)+256);	//sizeof ohci_hcca_desc + 256
	Host_memory_ptr = (char *) (((unsigned long)Host_memory_ptr + 0xFF) & ~0xFF);

	ohci_hcca = (ohci_hcca_desc *) Host_memory_ptr;
	
	for(i=0;i<32;i++)
		ohci_hcca->int_table[i] = 0;
	ohci_hcca->frame_no = 0;
	ohci_hcca->pad1 = 0;
	ohci_hcca->done_head=0;

	//EHCI
	ehci_peri_frame_list = (u32 *)0x60000000L;

	//Allocate RDC UDISK descriptor and set value
	//Device descriptor
	Host_memory_ptr = (char *)malloc(sizeof(std_dev_des));
	UDisk_dev_des = (std_dev_des *) Host_memory_ptr;
	
	UDisk_dev_des->bLength = 0x12;