usbhcd.c

RDC R2886 USB Ehci ohc测试源码,paradigm c++上运行测试

// USB Host Controller OHCI test pattern file
// 08/25/2003    Jeff

#include <systypes.h>					/* Paradigm C++ standard types */
#include <stdio.h>
#include <dos.h>
#include <alloc.h>
#include <embedded.h>
#include <string.h>
#include <conio.h>
#include "..\Include\USBHost.h"

#define EHCI_PORT_INIT	(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E|PORT_POWER)

extern ehci_registers __far *ehci_regs;
extern ehci_qh __far *ehci_Ep0;

extern ehci_qtd __far *ehci_Ctl_TD1;
extern ehci_qtd __far *ehci_Ctl_TD2;
extern ehci_qtd __far *ehci_Ctl_TD3;

extern setup_format __far *Ctl_Setup;
extern char __far *Ctl_Data;

extern std_dev_des __far *dev_des;
extern std_cfg_des __far *cfg_des;
extern std_if_des  __far *if_des;
extern std_edp_des __far *edp_des1;
extern std_edp_des __far *edp_des2;
extern std_edp_des __far *edp_des3;
extern char LANGID[4];
extern char String1[256];
extern char String2[256];
extern char String3[256];

extern std_dev_des __far *UDisk_dev_des;
extern std_cfg_des __far *UDisk_cfg_des;
extern std_if_des  __far *UDisk_if_des;
extern std_edp_des __far *UDisk_edp_des1;
extern std_edp_des __far *UDisk_edp_des2;
extern std_edp_des __far *UDisk_edp_des3;
extern char UDisk_LANGID[4];
extern char UDisk_String2[34];
extern char UDisk_String3[34];

extern int Do_TD_Complete;
extern u8 g_PortAttach;

/* +++++++++++++++++++++ USBHost.c +++++++++++++++++++++++++ */
BOOL Init_USB(void);

/* +++++++++++++++++++++ USBLib.c +++++++++++++++++++++++++ */
unsigned int UpperAddr (void far *p);
unsigned int LowerAddr (void far *p);
void DWordWrite(void far *p, u32 data);
void DWordWriteHL(void far *p, u16 dataH, u16 dataL);
u32 DWordRead(void far *p);
void mdelay(u16 ms);

/* +++++++++++++++++++++ USBUART.c +++++++++++++++++++++++++ */
void UART_Device_Descriptor(std_dev_des __far *p);
void UART_Configuration_Descriptor(std_cfg_des __far *p);
void UART_Interface_Descriptor(std_if_des __far *p);
void UART_Endpoint_Descriptor(std_edp_des __far *p, int num);
void UART_String_Descriptor(char *p, int string_num, int size);
char* Num_ASCII_W(char *p, int Data, BOOL AddPoint);
void UART_SendData(char* buf, int size);

extern int ControlCnt;
extern int Err_Cnt;

BOOL DoTest_Mode(int num)
{
	u32 temp;
	
	temp = DWordRead(&ehci_regs->port_status[USB_Port]);
	
	DWordWrite(&ehci_regs->command, 0x00080000L);
	do{} while((DWordRead(&ehci_regs->status) & STS_HALT) == 0);
	
	temp &= 0xFF00FFFFL;
	if(num == 1)
		temp |= PORT_Test_J;
	else if(num == 2)
		temp |= PORT_Test_K;
	else if(num == 3)
		temp |= PORT_Test_SE0_NAK;
	else if(num == 4)
		temp |= PORT_Test_Packet;
	else if(num == 5)
		temp |= PORT_Test_FORCE_ENABLE;
		
	DWordWrite(&ehci_regs->port_status[USB_Port], temp);
   //DWordWrite(&ehci_regs->port_status[USB_Port], temp);

	if((DWordRead(&ehci_regs->port_status[USB_Port]) & PORT_Test_FORCE_ENABLE) == PORT_Test_FORCE_ENABLE)
		DWordWrite(&ehci_regs->command, (0x00080000L | CMD_RUN));

	return TRUE;
}

BOOL EndTest_Mode()
{
	u32 temp;
	
	temp = DWordRead(&ehci_regs->port_status[USB_Port]);
	
	//Complete
	temp &= 0xFF00FFFFL;
	DWordWrite(&ehci_regs->port_status[USB_Port], temp);

	DWordWrite(&ehci_regs->command, 0x00080000L);
	do{} while((DWordRead(&ehci_regs->status) & STS_HALT) == 0);

	Init_USB();
	
	return TRUE;
}

void InitEndPoint0(void)
{
	char __far *Host_memory_ptr;

	//Allocate QH format structure
	Host_memory_ptr = (char *)malloc(sizeof(ehci_qh)+32);	//sizeof QH + 32
	Host_memory_ptr = (char *) (((unsigned long)Host_memory_ptr + 0x1F) & ~0x1F);

	ehci_Ep0 = (ehci_qh *) Host_memory_ptr;
	
	ehci_Ep0->hw_next = (UpperAddr(ehci_Ep0)<<16)|LowerAddr(ehci_Ep0)|QH_Typ_QH;
	ehci_Ep0->hw_info1 = QH_RL|0x00400000L|QH_HEAD|QH_DTC_TD|QH_EPS|QH_EndPt_0|0x00;	//MaxPckLen ..| device address
	ehci_Ep0->hw_info2 = QH_Mult;
	ehci_Ep0->hw_current = 0;
	ehci_Ep0->hw_qtd_next = 0x01;
	ehci_Ep0->hw_alt_next = 0x01;
	ehci_Ep0->hw_token = QH_IOC;
	ehci_Ep0->hw_buf[0] = 0;
	ehci_Ep0->hw_buf[1] = 0;
	ehci_Ep0->hw_buf[2] = 0;
	ehci_Ep0->hw_buf[3] = 0;
	ehci_Ep0->hw_buf[4] = 0;
	
	DWordWriteHL(&ehci_regs->async_next, UpperAddr(ehci_Ep0), LowerAddr(ehci_Ep0));
}

void InitControl3TD(void)
{
	char __far *Host_memory_ptr;
	
	//Allocate TD format structure
	Host_memory_ptr = (char *)malloc(sizeof(ehci_qtd)+32);	//sizeof ehci_qtd + 32
	Host_memory_ptr = (char *) (((unsigned long)Host_memory_ptr + 0x1F) & ~0x1F);
	ehci_Ctl_TD1 = (ehci_qtd *) Host_memory_ptr;
	
	//Allocate TD format structure
	Host_memory_ptr = (char *)malloc(sizeof(ehci_qtd)+32);	//sizeof ehci_qtd + 32
	Host_memory_ptr = (char *) (((unsigned long)Host_memory_ptr + 0x1F) & ~0x1F);
	ehci_Ctl_TD2 = (ehci_qtd *) Host_memory_ptr;

	//Allocate TD format structure
	Host_memory_ptr = (char *)malloc(sizeof(ehci_qtd)+32);	//sizeof ehci_qtd + 32
	Host_memory_ptr = (char *) (((unsigned long)Host_memory_ptr + 0x1F) & ~0x1F);
	ehci_Ctl_TD3 = (ehci_qtd *) Host_memory_ptr;
	
	Host_memory_ptr = (char *)malloc(sizeof(setup_format));
	Ctl_Setup = (setup_format *) Host_memory_ptr;

}

BOOL Do_Get_Device_Descriptor(void)
{
	//int i;
	//char *p, *q;
	
	//Setup Stage
	Ctl_Setup->bmRequestType = 0x80;
	Ctl_Setup->bRequest = 0x06;
	Ctl_Setup->wValue = 0x0100;
	Ctl_Setup->wIndex = 0x0000;
	Ctl_Setup->wLength = 0x0012;
	
	ehci_Ctl_TD1->hw_next = 0x01;
	ehci_Ctl_TD1->hw_alt_next = 0x01;
	ehci_Ctl_TD1->hw_buf[0] = (UpperAddr(Ctl_Setup) << 16) + LowerAddr(Ctl_Setup);
	ehci_Ctl_TD1->hw_token = 0x80000L|QTD_CERR_3|QTD_PID_SETUP|QTD_STS_ACTIVE;

	//Data Stage
	Ctl_Data = (char *)dev_des;
		
	ehci_Ctl_TD2->hw_next = 0x01;
	ehci_Ctl_TD2->hw_alt_next = 0x01;
	ehci_Ctl_TD2->hw_buf[0] = (UpperAddr(Ctl_Data) << 16) + LowerAddr(Ctl_Data);
	ehci_Ctl_TD2->hw_token = QTD_TOGGLE|0x400000L|QTD_CERR_3|QTD_PID_IN|QTD_STS_ACTIVE;

	ehci_Ctl_TD1->hw_next = (UpperAddr(ehci_Ctl_TD2) << 16) + LowerAddr(ehci_Ctl_TD2);

	//Status Stage
	ehci_Ctl_TD3->hw_next = 0x01;
	ehci_Ctl_TD3->hw_alt_next = 0x01;
	ehci_Ctl_TD3->hw_buf[0] = 0;
	ehci_Ctl_TD3->hw_token = QTD_TOGGLE|QTD_IOC|QTD_CERR_3|QTD_PID_OUT|QTD_STS_ACTIVE;
	
	ehci_Ctl_TD2->hw_next = (UpperAddr(ehci_Ctl_TD3) << 16) + LowerAddr(ehci_Ctl_TD3);
	
	//Write TD to QH, valid TD
	ehci_Ep0->hw_qtd_next = (UpperAddr(ehci_Ctl_TD1) << 16) + LowerAddr(ehci_Ctl_TD1);
	
	//Enable USB asynchronous Schedule
	Do_TD_Complete = 0;
	DWordWrite(&ehci_regs->command, (0x00080000L | CMD_ASE | CMD_RUN));
	
	//Wait TD complete
	do{} while(Do_TD_Complete == 0);
	
	//Check TD status
	if(((ehci_Ctl_TD1->hw_token & 0x7E) != 0) ||
		((ehci_Ctl_TD2->hw_token & 0x7E) != 0) || ((ehci_Ctl_TD3->hw_token & 0x7E) != 0))
		//return FALSE;
      Err_Cnt++;

	//Check device descriptor data
	/*p = (char *) dev_des;
	q = (char *) UDisk_dev_des;
	for(i=0;i<18;i++)
		if(*p++ != *q++)
			return FALSE;*/
			
	return TRUE;
}

BOOL InitEDTD()
{
	InitEndPoint0();
	InitControl3TD();

	return TRUE;
}

BOOL SetAddress(int Address)
{
	//Setup Stage
	Ctl_Setup->bmRequestType = 0x00;
	Ctl_Setup->bRequest = 0x05;
	Ctl_Setup->wValue = Address;
	Ctl_Setup->wIndex = 0x0000;
	Ctl_Setup->wLength = 0x0000;
	
	ehci_Ctl_TD1->hw_next = 0x01;
	ehci_Ctl_TD1->hw_alt_next = 0x01;
	ehci_Ctl_TD1->hw_buf[0] = (UpperAddr(Ctl_Setup) << 16) + LowerAddr(Ctl_Setup);
	ehci_Ctl_TD1->hw_token = 0x80000L|QTD_CERR_3|QTD_PID_SETUP|QTD_STS_ACTIVE;
	
	//Status Stage
	ehci_Ctl_TD3->hw_next = 0x01;
	ehci_Ctl_TD3->hw_alt_next = 0x01;
	ehci_Ctl_TD3->hw_buf[0] = 0;
	ehci_Ctl_TD3->hw_token = QTD_TOGGLE|QTD_IOC|QTD_CERR_3|QTD_PID_IN|QTD_STS_ACTIVE;
	
	ehci_Ctl_TD1->hw_next = (UpperAddr(ehci_Ctl_TD3) << 16) + LowerAddr(ehci_Ctl_TD3);
	
	Do_TD_Complete = 0;
	ehci_Ep0->hw_qtd_next = (UpperAddr(ehci_Ctl_TD1) << 16) + LowerAddr(ehci_Ctl_TD1);

	do{} while(Do_TD_Complete == 0);

//Sten
	if(((ehci_Ctl_TD1->hw_token & 0x7E) != 0) || ((ehci_Ctl_TD3->hw_token & 0x7E) != 0))
		//return FALSE;
      Err_Cnt++;

	ehci_Ep0->hw_info1 = QH_RL|0x00400000L|QH_HEAD|QH_DTC_TD|QH_EPS|QH_EndPt_0|QH_DAddr;	//MaxPckLen ..| device address

	return TRUE;
}

BOOL InitControlTransfer()
{
	//Set Ep0's address to 0
	ehci_Ep0->hw_info1 = QH_RL|0x00400000L|QH_HEAD|QH_DTC_TD|QH_EPS|QH_EndPt_0|0x00;	//MaxPckLen ..| device address

	if(Do_Get_Device_Descriptor() == FALSE)
		return FALSE;

	//Port reset +++++++++++++
   mdelay(100);
	g_PortAttach = 0;
	DWordWrite(&ehci_regs->port_status[USB_Port], (EHCI_PORT_INIT|PORT_RESET));
	mdelay(50);
	DWordWrite(&ehci_regs->port_status[USB_Port], (EHCI_PORT_INIT));

	//Wait reset complete
	do{} while((DWordRead(&ehci_regs->port_status[USB_Port]) & PORT_RESET) == PORT_RESET);
	if((DWordRead(&ehci_regs->port_status[USB_Port]) & (PORT_CONNECT|PORT_PE)) == (PORT_CONNECT|PORT_PE))
		g_PortAttach = 1;
	else
		return FALSE;
	
	//Set a Address to device
	if(SetAddress(1) == FALSE)
		return FALSE;
	
	return TRUE;
}

/*-------------------------------------------------------------------------*
 * Control Transfer
 *-------------------------------------------------------------------------*/
BOOL Get_Device_Descriptor(u32 size)
{
	//int i;
	//char *p, *q;
	u32 temp;
	
	dev_des->bLength = 0x20;

	//Setup Stage
	Ctl_Setup->bmRequestType = 0x80;
	Ctl_Setup->bRequest = 0x06;
	Ctl_Setup->wValue = 0x0100;
	Ctl_Setup->wIndex = 0x0000;
	Ctl_Setup->wLength = (u16)size;
	
	ehci_Ctl_TD1->hw_next = 0x01;
	ehci_Ctl_TD1->hw_alt_next = 0x01;
	ehci_Ctl_TD1->hw_buf[0] = (UpperAddr(Ctl_Setup) << 16) + LowerAddr(Ctl_Setup);
	ehci_Ctl_TD1->hw_token = 0x80000L|QTD_CERR_3|QTD_PID_SETUP|QTD_STS_ACTIVE;

	//Data Stage
	Ctl_Data = (char *)dev_des;

	ehci_Ctl_TD2->hw_next = 0x01;
	ehci_Ctl_TD2->hw_alt_next = 0x01;
	ehci_Ctl_TD2->hw_buf[0] = (UpperAddr(Ctl_Data) << 16) + LowerAddr(Ctl_Data);
	temp = size << 16;
	ehci_Ctl_TD2->hw_token = QTD_TOGGLE|temp|QTD_CERR_3|QTD_PID_IN|QTD_STS_ACTIVE;

	ehci_Ctl_TD1->hw_next = (UpperAddr(ehci_Ctl_TD2) << 16) + LowerAddr(ehci_Ctl_TD2);

	//Status Stage
	ehci_Ctl_TD3->hw_next = 0x01;
	ehci_Ctl_TD3->hw_alt_next = 0x01;
	ehci_Ctl_TD3->hw_buf[0] = 0;
	ehci_Ctl_TD3->hw_token = QTD_TOGGLE|QTD_IOC|QTD_CERR_3|QTD_PID_OUT|QTD_STS_ACTIVE;
	
	ehci_Ctl_TD2->hw_next = (UpperAddr(ehci_Ctl_TD3) << 16) + LowerAddr(ehci_Ctl_TD3);
	
	//Write TD to QH, valid TD
	Do_TD_Complete = 0;
	ehci_Ep0->hw_qtd_next = (UpperAddr(ehci_Ctl_TD1) << 16) + LowerAddr(ehci_Ctl_TD1);

	do{} while(Do_TD_Complete == 0);

//Sten
	if(((ehci_Ctl_TD1->hw_token & 0x7E) != 0) ||
		((ehci_Ctl_TD2->hw_token & 0x7E) != 0) || ((ehci_Ctl_TD3->hw_token & 0x7E) != 0))
		//return FALSE;
      Err_Cnt++;

	/*p = (char *) dev_des;
	q = (char *) UDisk_dev_des;
	for(i=0;i<sizeof(std_dev_des);i++)
		if(*p++ != *q++)
			return FALSE; */

	return TRUE;
}

BOOL Get_Configuration_Desc(int Length)
{
	//int i;
	u32 temp;	
	//char *p, *q;
	
	cfg_des->bLength = 0x12;
	
	//Setup Stage