📄 msp430x20x3_usi_06.s43
字号:
;******************************************************************************
; MSP430F20xx Demo - I2C Master Receiver, single byte
;
; Description: I2C Master communicates with I2C Slave using
; the USI. Slave data should increment from 0x00 with each transmitted byte
; which is verified by the Master.
; LED off for address or data Ack; LED on for address or data NAck.
; ACLK = n/a, MCLK = SMCLK = Calibrated 1MHz
;
; ***THIS IS THE MASTER CODE***
;
; Slave Master
; (msp430x20x3_usi_09.s43)
; MSP430F20x2/3 MSP430F20x2/3
; ----------------- -----------------
; /|\| XIN|- /|\| XIN|-
; | | | | | |
; --|RST XOUT|- --|RST XOUT|-
; | | | |
; LED <-|P1.0 | | |
; | | | P1.0|-> LED
; | SDA/P1.7|------->|P1.7/SDA |
; | SCL/P1.6|<-------|P1.6/SCL |
;
; Note: internal pull-ups are used in this example for SDA & SCL
;
; P. Thanigai
; Texas Instruments Inc.
; May 2007
; Built with IAR Embedded Workbench Version: 3.42A
;******************************************************************************
#include "msp430x20x2.h"
#define I2CState R4
#define slav_data R5
#define slav_add R6
;-------------------------------------------------------------------------------
RSEG CSTACK ; Define stack segment
;-------------------------------------------------------------------------------
RSEG CODE ; Assemble to Flash memory
EVEN
;-------------------------------------------------------------------------------
RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop watchdog timer
SetupDCO mov.b &CALBC1_1MHZ,&BCSCTL1 ; Load DCO constants
mov.b &CALDCO_1MHZ,&DCOCTL
SetupP1 mov.b #0xC0,&P1OUT ; P1.6&P1.7 Pullups
bis.b #0xC0,&P1REN ; P1.6&P1.7 Pullups
mov.b #0xFF,&P1DIR ; unused pins as output
SetupP2 mov.b #0x00,&P2OUT
mov.b #0xFF,&P2DIR
SetupUSI mov.b #USIPE6+USIPE7+USIMST+USISWRST,&USICTL0 ;Port, I2C master
mov.b #USIIE+USII2C,&USICTL1 ; Counter interrupt, enable I2C
mov.b #USIDIV_3+USISSEL_2+USICKPL,&USICKCTL ; SCL=SMCLK/8(~120KHz)
bis.b #USIIFGCC,&USICNT ;
bic.b #USISWRST,&USICTL0 ; Enable USI
bic.b #USIIFG,&USICTL1 ; Clear pending flag
clr.w I2CState
clr.b slav_data
mov.b #0x91,slav_add
Mainloop bis.b #USIIFG,&USICTL1 ; Set flag and start communication
bis.w #LPM0+GIE,SR ; Enter LPM0, enable interrupts
nop ; Used for debugger
call #Delay ; Delay between commn. cycles
jmp Mainloop
;-------------------------------------------------------------------------------
USI_ISR ;
;-------------------------------------------------------------------------------
add.w I2CState,PC ; I2C State Machine
jmp STATE0
jmp STATE2
jmp STATE4
jmp STATE6
jmp STATE8
jmp STATE10
STATE0
bis.b #0x01,&P1OUT ; LED on: sequence start
clr.b &USISRL ; Generate start condition
bis.b #USIGE+USIOE,&USICTL0 ;
bic.b #USIGE,&USICTL0 ; & send address to slave
mov.b slav_add,&USISRL ; and transmit address R/W =1
mov.b &USICNT,R8 ; Bit counter = 8, Tx adress
and.b #0xE0,R8
add.b #0x08,R8
mov.b R8,&USICNT
mov.w #2,I2CState ; Go to next state rx address (N)ACK
bic.b #USIIFG,&USICTL1 ; clear pending flag
reti
STATE2 ; Receive Address Ack/Nack bit
bic.b #USIOE,&USICTL0 ; SDA = input
bis.b #0x01,&USICNT ; Bit counter = 1, rx (N)ACK
mov.w #4,I2CState ; Go to next state, chk (N)ACK
bic.b #USIIFG,&USICTL1
reti
STATE4 ; Process Address (N)Ack & data Rx
bit.b #0x01,&USISRL ; if NACK received
jnc Data_Rx ; else ACK received
bis.b #USIOE,&USICTL0
clr.b &USISRL
bis.b #0x01,&USICNT ; bit counter = 1, SCL high, SDA low
mov.w #10,I2CState ; Go to next state, generate stop
bis.b #0x01,&P1OUT ; Turn on LED : error
bic.b #USIIFG,&USICTL1
reti
Data_Rx
bis.b #8,&USICNT ; bit counter = 8, Rx data
mov.w #6,I2CState ; goto next state: Test data, (N)ACK
bic.b #0x1,&P1OUT ; LED off
bic.b #USIIFG,&USICTL1
reti
STATE6 ; Send Data (N)Ack bit
bis.b #USIOE,&USICTL0 ; SDA = output
cmp.b slav_data,&USISRL ; if data valid
jnz Data_NACK ; data invalid , goto NACK loop
clr.b &USISRL ; send ACK
inc.b slav_data ; Increment slave data
bic.b #0x01,&P1OUT ; LED off
jmp STATE6_Exit
Data_NACK
mov.b #0xFF,&USISRL ; Send NACK
bis.b #0x1,&P1OUT ; LED on:error
STATE6_Exit
bis.b #0x1,&USICNT ; Bit counter = 1, send NACK bit
mov.w #8,I2CState ; goto next state, prep stop
bic.b #USIIFG,&USICTL1
reti
STATE8 ; Pre stop condition
bis.b #USIOE,&USICTL0 ; SDA =output
clr.b &USISRL
bis.b #0x01,&USICNT ; Bit counter = 1, SCL high, SDA low
mov.w #10,I2CState ; Go to next state, generate stop
bic.b #USIIFG,&USICTL1
reti
STATE10 ; Generate stop condition
mov.b #0xFF,&USISRL ; USISRL=1 to release SDA
bis.b #USIGE,&USICTL0 ; Transparent latch enabled
bic.b #USIGE+USIOE,&USICTL0 ; Latch/SDA output disabled
mov.w #0,I2CState ; Reset state machine for next Tx
bic.w #LPM0,0(SP) ; Exit active for next transfer
bic.b #USIIFG,&USICTL1
reti
;-------------------------------------------------------------------------------
Delay ; Delay between communication cycles
;-------------------------------------------------------------------------------
mov.w #0xFFFF,R7
DL1 dec.w R7
jnz DL1
ret
;-------------------------------------------------------------------------------
; Interrupt Vectors Used MSP430x2013
;-------------------------------------------------------------------------------
COMMON INTVEC
ORG RESET_VECTOR ; MSP430 RESET Vector
DW RESET ;
ORG USI_VECTOR ; USICNT
DW USI_ISR ;
END⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -