📄 initsys.lst
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C51 COMPILER V6.12 INITSYS 07/06/2003 16:32:57 PAGE 1
C51 COMPILER V6.12, COMPILATION OF MODULE INITSYS
OBJECT MODULE PLACED IN initsys.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE initsys.c DB OE
stmt level source
1 /*=========================================================================================
2 INITIALIZATION RUTINE
3 ===========================================================================================
4 AHTH: GZG
5 DATE:
6 COMMENT:
7 ===========================================================================================*/
8 /*----------------------------------------INCLUDE-----------------------------------------*/
9 #include <c8051f020.h>
10
11 #define TC_100ms 16000
12 /*---------------------------------------FUNCTION DECLARING------------------------------*/
13 extern void delay(int t);
14 //extern void in_eeprom();
15 //extern void writeCmd (unsigned char command);
16 //extern void delayMS(unsigned char MS);
17 /*---------------------------------------GLOBLE DECLARING--------------------------------*/
18 //extern unsigned int xdata canmodify_package[];
19 //extern long int transfer_ad;
20 //extern long int time_data;
21 /*---------------------------------------16BIT SFR DEFINE--------------------------------*/
22 sfr16 TMR3=0x94;
23 sfr16 TMR3RL=0x92;
24 //sbit p3_3=P3^3;
25 //sbit p3_4=P3^4;
26 //sbit p3_5=P3^5;
27 //sbit p3_6=P3^6;
28 //sbit p1_7=P1^7;
29 //sbit CS=P1^7;
30 //sbit D_ready=P3^0;
31 void initsys(void)
32 //sbit CS=P1^7;
33
34 {
35 1 // unsigned int xdata *pwrite;
36 1 // unsigned int code *pread;
37 1 // unsigned char i ;
38 1 // unsigned char i1;
39 1 WDTCN = 0xde; //stop the wdt
40 1 WDTCN = 0xad;
41 1
42 1 /*-----------------------------------------------------------------------------------------
43 1 DEFINE IO OSC
44 1 -----------------------------------------------------------------------------------------*/
45 1 OSCXCN=0x66;
46 1 delay(10000);
47 1 delay(10000);
48 1 while(OSCXCN&0x80!=0x80);
49 1 OSCICN|=0x08;
50 1 /*----------------------------------------------------------------------------------------
51 1 DEFINE IO uart0 uart1 spi
52 1 ----------------------------------------------------------------------------------------*/
53 1
54 1 XBR0=0x04; //uart0 and spi
55 1 XBR1=0x00;
C51 COMPILER V6.12 INITSYS 07/06/2003 16:32:57 PAGE 2
56 1 XBR2=0x44;
57 1
58 1 //P0MDOUT=0xff;
59 1 P1MDIN=0xff;
60 1 P1MDOUT=0xff;
61 1 P2MDOUT=0xff;
62 1 P3MDOUT=0xff;
63 1 //P3MDOUT&=~0x78;
64 1 //P3MDOUT&=~0x01;
65 1 //D_ready=1;
66 1
67 1 // SPI0CFG=0x87;//8_bit onetime
68 1 //SPI0CN=0X03;//make it master stype
69 1
70 1 //SPI0CN|=0X01;//enable spi
71 1
72 1 // SPI0CKR = 0x01;
73 1 // CS=0;
74 1
75 1 //p1_7=1;
76 1
77 1 //p3_3=0;
78 1 //p3_4=0;
79 1 //p3_5=0;
80 1 //p3_6=0;
81 1 /*----------------------------------------------------------------------------------------
82 1 DEFINE DA AND VREF
83 1 ----------------------------------------------------------------------------------------*/
84 1 REF0CN=0x02;
85 1 DAC0CN=0x80;
86 1
87 1 //DAC0L=0xff;
88 1 //DAC0H=0xff;
89 1
90 1 /*----------------------------------------------------------------------------------------
91 1 DEFINE T1
92 1 -----------------------------------------------------------------------------------------*/
93 1 /* TMOD=0x10;
94 1 CKCON=0x10;
95 1 TH1=0x00;
96 1 TL1=0x00;
97 1 TR1=1;*/
98 1 TMOD=0X10;
99 1 CKCON=0X10;
100 1 TH1=0xf0;
101 1 TL1=0;
102 1 TR1=1;
103 1
104 1 /*----------------------------------------------------------------------------------------
105 1 DEFINE T3
106 1 ----------------------------------------------------------------------------------------*/
107 1 TMR3CN&=~0x80;
108 1 //TMR3CN|=0x02;
109 1 // TMR3RLL= 0xb0;
110 1 TMR3RLL= 0xaf;
111 1 TMR3RLH=0x3c;
112 1 //TMR3=0xffff;
113 1 EIE2&=~0x01;
114 1 TMR3CN|=0x04;
115 1
116 1 /*---------------------------------------------------------------------------------------
117 1 DEFINE IO FOO5
C51 COMPILER V6.12 INITSYS 07/06/2003 16:32:57 PAGE 3
118 1 ----------------------------------------------------------------------------------------*/
119 1 // PRT3CF=0xff;
120 1 //PRT2CF=0xff;
121 1 //P3=0xff;
122 1 //PRT1CF=0x00;
123 1 // PRT0CF=0xff;
124 1 //P0=0xff;
125 1 /*****************************
126 1 DEFINE AD
127 1 *****************************/
128 1 AMX0CF = 0x00; //select the single channle
129 1 AMX0SL = 0x00; //delect the an0 channel
130 1 ADC0CF = 0x00;
131 1 ADC0CN=0x90;
132 1
133 1 /*DAC0CN = 0x80; // DAC0 Control Register
134 1 REF0CN=0x03;
135 1 WDTCN = 0xde; //stop the wdt
136 1 WDTCN = 0xad;
137 1 TMR3CN = 0x00; // stop Timer3
138 1 TMR3RLH = ((-TC_100ms >> 8) & 0xff);
139 1 TMR3RLL = (-TC_100ms & 0xff);
140 1 TMR3H = 0xff; // init Timer3 to reload immediately
141 1 TMR3L = 0xff;
142 1 // EIE2 = 0x01; // enable Timer3 OVR interrupt
143 1 TMR3CN = 0x04; // start Timer3*/
144 1 /*----------------------------------------------------------------------------------------
145 1 define uart0 and timer2
146 1 -----------------------------------------------------------------------------------------*/
147 1 SCON0=0x50;//THE BANDRAT IS 2400；AND THE TIMER IS TIMER2；
148 1 PCON=0x00;
149 1 //TL1=0x00;TH1=0x00;
150 1 //P3&=~0x02;//R enable
151 1 //SCON1=0xd0;
152 1 T2CON=0x30;
153 1 RCAP2H=0xff;
154 1 RCAP2L=0xb1;
155 1 T2CON|=0x04;
156 1 TR1=1;
157 1 // TI0=1;
158 1
159 1
160 1 //RI0=0;
161 1 /*-----------------------------------------------------------------------------------------
162 1 DEFINE uart1 and timer4
163 1 ------------------------------------------------------------------------------------------*/
164 1 P3&=~0x02; //R enable
165 1 SCON1=0xd0;
166 1 T4CON=0x30;
167 1 RCAP4H=0xff;
168 1 RCAP4L=0xb1;
169 1 T4CON|=0x04;
170 1
171 1 /*----------------------------------------------------------------------------------------
172 1 eeprom init and get the current value
173 1 -----------------------------------------------------------------------------------------*/
174 1 /* in_eeprom();
175 1
176 1 WDTCN=0xde; //stop watch dog
177 1 WDTCN=0xad;
178 1
179 1 FLSCL|=0x01;
C51 COMPILER V6.12 INITSYS 07/06/2003 16:32:57 PAGE 4
180 1 PSCTL|=0X02;
181 1 PSCTL|=0X01;
182 1
183 1 pwrite=0xa000;
184 1 *pwrite=0;
185 1 PSCTL&=~0X02;
186 1 for(i=0;i<19;i++)
187 1 {
188 1 *pwrite++=canmodify_package[i];
189 1
190 1 }
191 1 PSCTL&=~0x01;
192 1
193 1 */
194 1
195 1 // pread=0xa000; //read the current value
196 1 //for(i1=0;i1<19;i1++)
197 1 //{
198 1 //canmodify_package[i1]=*pread++;
199 1 //}
200 1 /*-----------------------------------------------------------------------------------------
201 1 INITIALIZATION OF AD7705
202 1 ------------------------------------------------------------------------------------------*/
203 1 // if(canmodify_package[5]==1)
204 1 // {
205 1 // CS=0;
206 1 //init3();
207 1 //delayMS (50);
208 1 //delay(100);
209 1 //writeCmd (0x20); /*write to communications register setting chan_*/
210 1 /*nel to be Ain1(+)/Ain1(-), setting up next op_*/
211 1 /*eration to be a write to the clock register */
212 1
213 1 //writeCmd (0x00); /* the datasheet is wrong!! */
214 1 /*write to clock register, set the clock bits to*/
215 1 /*be: Master clock enabled, 4.9152MHz clock, and*/
216 1 /*set output rate to 50Hz */
217 1
218 1 // writeCmd (0x10); /*write to communications register, set channel */
219 1 /*to be Ain1(+)/Ain1(-), setting up next operat_*/
220 1 /*ion to be a write to the setup register */
221 1
222 1 // writeCmd (0x44); /*write to setup register, clear FSYNC, set gain*/
223 1 /*to 1, monopolar mode, buffer off,and perform a*/
224 1 // } /*self calibration */
225 1 /*----------------------------------------------------------------------------------------
226 1 DEFINE interrupt
227 1 -------------------------------------------------------------------------------------------*/
228 1 IE|=0x80;
229 1 EIP2|=0x01;//set the time3 first
230 1 EIE2|=0x01;//enable time3 interrupt
231 1
232 1 IE|=0x08;//enable time1 interrupt
233 1 EIE2|=0x40;//enable uart1 interrpt
234 1 //EIP2=0x40; //set the uart1 first
235 1 IE|=0x10;
236 1 // transfer_ad=0;
237 1 ES0=1;
238 1 //p3_3=1;
239 1 // p3_3=1;
240 1 // p3_4=1;
241 1 // p3_5=1;
C51 COMPILER V6.12 INITSYS 07/06/2003 16:32:57 PAGE 5
242 1 // p3_6=1;
243 1
244 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 148 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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