dsp28_sysctrl.c

DSP2812 GPIO口读数的工程文件

#include	"DSP281x_Device.h"

void InitSysCtrl(void)
{
   	Uint16 i;
   	
   	EALLOW;
   
// On TMX samples, to get the best performance of on chip RAM blocks M0/M1/L0/L1/H0 internal
// control registers bit have to be enabled. The bits are in Device emulation registers.
//   DevEmuRegs.M0RAMDFT = 0x0300;
//   DevEmuRegs.M1RAMDFT = 0x0300;
//   DevEmuRegs.L0RAMDFT = 0x0300;
//   DevEmuRegs.L1RAMDFT = 0x0300;
//   DevEmuRegs.H0RAMDFT = 0x0300;
   
           
// Disable watchdog module
   	SysCtrlRegs.WDCR= 0x0068;

/** Initalize PLL **/
   	SysCtrlRegs.PLLCR.all = 0xA;				//5 times of the input soc clk
   	for(i= 0; i< 5000; i++){} 				// Wait for PLL to lock   
   
/*** Configure the clocks ***/
	SysCtrlRegs.HISPCP.all = 0x0000;		// Hi-speed periph clock prescaler, HSPCLK=SYSCLKOUT/1
	SysCtrlRegs.LOSPCP.all = 0x0002;		// Lo-speed periph clock prescaler, LOSPCLK=SYSCLKOUT/4

//	SysCtrlRegs.PCLKCR.bit.ECANENCLK = 1;	// SYSCLK to CAN enabled
//	SysCtrlRegs.PCLKCR.bit.MCBSPENCLK = 1;	// LSPCLK to McBSP enabled
//	SysCtrlRegs.PCLKCR.bit.SCIBENCLK = 1;	// LSPCLK to SCIB enabled
//	SysCtrlRegs.PCLKCR.bit.SCIAENCLK = 1;	// LSPCLK to SCIA enabled
//	SysCtrlRegs.PCLKCR.bit.SPIENCLK = 1;	// LSPCLK to SPI enabled
	SysCtrlRegs.PCLKCR.bit.ADCENCLK = 1;	// HSPCLK to ADC enabled
	SysCtrlRegs.PCLKCR.bit.EVBENCLK = 1;	// HSPCLK to EVB enabled
	SysCtrlRegs.PCLKCR.bit.EVAENCLK = 1;	// HSPCLK to EVA enabled
	
/*** Configure the low-power modes ***/
	SysCtrlRegs.LPMCR0.all = 0x00FC;		// LPMCR0 set to default value
	SysCtrlRegs.LPMCR1.all = 0x0000;		// LPMCR1 set to default value
								
   	EDIS;
	
}

//---------------------------------------------------------------------------
// KickDog: 
//---------------------------------------------------------------------------
// This function resets the watchdog timer.
// Enable this function for using KickDog in the application 
/*
void KickDog(void)
{
    EALLOW;
    SysCtrlRegs.WDKEY = 0x0055;
    SysCtrlRegs.WDKEY = 0x00AA;
    EDIS;
}
*/	
	
//===========================================================================
// No more.
//===========================================================================