v3k_fram_watch_sdcc.rel

这是ramtron公司的铁电单片机的开发程序

;!FILE V3K_FRAM_Watch_SDCC.asm
XH
H 16 areas 14B global symbols
M V3K_FRAM_Watch_SDCC
O -mmcs51 --model-small
S G$PWMTMRF$0$0 Def00AE
S G$PERIPHEN2$0$0 Def00F5
S G$TH1$0$0 Def008D
S _P1 Def0090
S G$TH2$0$0 Def008F
S _P2 Def00A0
S _B Def00F0
S _I2CSTATUS Def00D4
S G$INTEN1$0$0 Def0088
S _SP Def0081
S _P3 Def00B0
S G$AURES0$0$0 Def00B4
S G$INTEN2$0$0 Def00A8
S G$T2CLKCFG$0$0 Def009D
S G$TL0$0$0 Def008A
S _T0CON Def009A
S _P4 Def00C0
S _AUSHIFTCFG Def00C1
S G$AURES1$0$0 Def00B5
S G$TL1$0$0 Def008C
S _P5 Def0098
S _T1CON Def009B
S G$AURES2$0$0 Def00B6
S G$SPIRXTX0$0$0 Def00C4
S G$TL2$0$0 Def008E
S _T2CON Def009C
S _P6 Def00C8
S G$AURES3$0$0 Def00B7
S G$SPIRXTX1$0$0 Def00C5
S _ACC Def00E0
S _PWMEN Def00AA
S _AUA0 Def00A2
S __mcs51_genRAMCLEAR Ref0000
S G$I2CRXTX$0$0 Def00D5
S G$SPIRXTX2$0$0 Def00C6
S _UART0BRH Def00A5
S _AUA1 Def00A3
S _AUB0 Def00B2
S G$SPIRXTX3$0$0 Def00C7
S G$DEVIOMAP$0$0 Def00E1
S _UART0BUF Def00A3
S _UART1BRH Def00B4
S _AUC0 Def00A4
S _AUB1 Def00B3
S _PWC0CFG Def009E
S _UART1BUF Def00B2
S _AUC1 Def00A5
S G$P0PINCFG$0$0 Def00F9
S _PWC1CFG Def009F
S _AUC2 Def00A6
S _AUB0DIV Def00B1
S G$P1PINCFG$0$0 Def00FA
S G$GENINTEN$0$0 Def00E8
S _DPH0 Def0083
S _XMEMCTRL Def00D9
S _UART0BRL Def00A4
S _AUC3 Def00A7
S G$P2PINCFG$0$0 Def00FB
S _DPH1 Def0085
S _UART1BRL Def00B3
S G$P3PINCFG$0$0 Def00FC
S G$DEVCLKCFG1$0$0 Def00F2
S G$IPINSENS1$0$0 Def00E6
S G$PSW$0$0 Def00D0
S _IPININV1 Def00D6
S _DEVMEMCFG Def00F6
S _PWMDATA Def00AC
S G$P4PINCFG$0$0 Def00FD
S G$DEVCLKCFG2$0$0 Def00F3
S G$IPINSENS2$0$0 Def00E7
S _IPININV2 Def00D7
S _PORTINEN Def00F7
S _PWMLDPOL Def00AB
S G$UART0CFG$0$0 Def00A2
S G$P5PINCFG$0$0 Def00FE
S _DPL0 Def0082
S _PCON Def0087
S _SPISTATUS Def00C9
S G$UART1CFG$0$0 Def00B1
S G$P6PINCFG$0$0 Def00FF
S _DPL1 Def0084
S _T0T1CLKCFG Def0099
S G$P0$0$0 Def0080
S __XPAGE Def00F1
S _I2CCONFIG Def00D1
S G$P1$0$0 Def0090
S _FPICONFIG Def00E9
S G$I2CSTATUS$0$0 Def00D4
S G$B$0$0 Def00F0
S G$P2$0$0 Def00A0
S G$P3$0$0 Def00B0
S G$SP$0$0 Def0081
S _PORTCHG Def00B9
S _UART0INT Def00A1
S G$AUSHIFTCFG$0$0 Def00C1
S G$P4$0$0 Def00C0
S G$T0CON$0$0 Def009A
S _UART1INT Def00B0
S G$T1CON$0$0 Def009B
S G$P5$0$0 Def0098
S _T0T1CFG Def0089
S G$P6$0$0 Def00C8
S G$T2CON$0$0 Def009C
S _PWMTMREN Def00AD
S G$AUA0$0$0 Def00A2
S G$PWMEN$0$0 Def00AA
S G$ACC$0$0 Def00E0
S _IPINFLAG1 Def00B8
S _I2CIDCFG Def00D3
S G$AUB0$0$0 Def00B2
S G$AUA1$0$0 Def00A3
S G$UART0BRH$0$0 Def00A5
S _IPINFLAG2 Def00D8
S G$AUB1$0$0 Def00B3
S G$AUC0$0$0 Def00A4
S G$UART1BRH$0$0 Def00B4
S G$UART0BUF$0$0 Def00A3
S _UART0EXT Def00A6
S _AUCONFIG1 Def00C2
S G$AUC1$0$0 Def00A5
S G$UART1BUF$0$0 Def00B2
S G$PWC0CFG$0$0 Def009E
S _RCAP0H Def0093
S _PWMCLKCFG Def00AF
S _UART1EXT Def00B5
S _AUCONFIG2 Def00C3
S G$AUB0DIV$0$0 Def00B1
S G$AUC2$0$0 Def00A6
S G$PWC1CFG$0$0 Def009F
S _WDTCFG Def0091
S _RCAP1H Def0095
S G$AUC3$0$0 Def00A7
S G$UART0BRL$0$0 Def00A4
S G$XMEMCTRL$0$0 Def00D9
S G$DPH0$0$0 Def0083
S _RCAP2H Def0097
S _FPICLKSPD Def00EE
S G$UART1BRL$0$0 Def00B3
S G$DPH1$0$0 Def0085
S _frambase Def8000
S _FPIDATAH Def00ED
S _SPICTRL Def00C1
S G$PWMDATA$0$0 Def00AC
S G$DEVMEMCFG$0$0 Def00F6
S G$IPININV1$0$0 Def00D6
S _RCAP0L Def0092
S _FPIADDRH Def00EB
S _SPICONFIG Def00C2
S G$PWMLDPOL$0$0 Def00AB
S G$PORTINEN$0$0 Def00F7
S G$IPININV2$0$0 Def00D7
S _RCAP1L Def0094
S _AUPREV0 Def00C4
S G$SPISTATUS$0$0 Def00C9
S G$PCON$0$0 Def0087
S G$DPL0$0$0 Def0082
S _RCAP2L Def0096
S _INTSRC1 Def00E4
S _PWMCFG Def00A9
S _AUPREV1 Def00C5
S G$DPL1$0$0 Def0084
S _INTSRC2 Def00E5
S _FPIDATAL Def00EC
S _AUPREV2 Def00C6
S _FPIADDRL Def00EA
S _I2CTIMING Def00D2
S _AUPREV3 Def00C7
S G$T0T1CLKCFG$0$0 Def0099
S _DPS Def0086
S _INTPRI1 Def00E2
S _SPISIZE Def00C3
S _FRAMCFG1 Def00DC
S G$I2CCONFIG$0$0 Def00D1
S G$_XPAGE$0$0 Def00F1
S _INTPRI2 Def00E3
S _FRAMCFG2 Def00DD
S G$FPICONFIG$0$0 Def00E9
S _MPAGE Def00F1
S G$UART0INT$0$0 Def00A1
S G$PORTCHG$0$0 Def00B9
S G$UART1INT$0$0 Def00B0
S _TH0 Def008B
S _PERIPHEN1 Def00F4
S _USERFLAGS Def00F8
S __mcs51_genXINIT Ref0000
S G$T0T1CFG$0$0 Def0089
S _TH1 Def008D
S _PERIPHEN2 Def00F5
S _PWMTMRF Def00AE
S G$PWMTMREN$0$0 Def00AD
S _TH2 Def008F
S G$I2CIDCFG$0$0 Def00D3
S G$IPINFLAG1$0$0 Def00B8
S _INTEN1 Def0088
S G$IPINFLAG2$0$0 Def00D8
S _TL0 Def008A
S _T2CLKCFG Def009D
S _INTEN2 Def00A8
S _AURES0 Def00B4
S G$AUCONFIG1$0$0 Def00C2
S G$UART0EXT$0$0 Def00A6
S _TL1 Def008C
S _AURES1 Def00B5
S G$AUCONFIG2$0$0 Def00C3
S G$UART1EXT$0$0 Def00B5
S G$PWMCLKCFG$0$0 Def00AF
S G$RCAP0H$0$0 Def0093
S _TL2 Def008E
S _SPIRXTX0 Def00C4
S _AURES2 Def00B6
S G$RCAP1H$0$0 Def0095
S G$WDTCFG$0$0 Def0091
S _SPIRXTX1 Def00C5
S _AURES3 Def00B7
S G$FPICLKSPD$0$0 Def00EE
S G$RCAP2H$0$0 Def0097
S _SPIRXTX2 Def00C6
S _I2CRXTX Def00D5
S G$frambase$0$0 Def8000
S G$SPICTRL$0$0 Def00C1
S G$FPIDATAH$0$0 Def00ED
S _DEVIOMAP Def00E1
S _SPIRXTX3 Def00C7
S G$SPICONFIG$0$0 Def00C2
S G$FPIADDRH$0$0 Def00EB
S G$RCAP0L$0$0 Def0092
S G$AUPREV0$0$0 Def00C4
S G$RCAP1L$0$0 Def0094
S _P0PINCFG Def00F9
S G$AUPREV1$0$0 Def00C5
S G$PWMCFG$0$0 Def00A9
S G$INTSRC1$0$0 Def00E4
S G$RCAP2L$0$0 Def0096
S _GENINTEN Def00E8
S _P1PINCFG Def00FA
S G$AUPREV2$0$0 Def00C6
S G$FPIDATAL$0$0 Def00EC
S G$INTSRC2$0$0 Def00E5
S _P2PINCFG Def00FB
S G$AUPREV3$0$0 Def00C7
S G$I2CTIMING$0$0 Def00D2
S G$FPIADDRL$0$0 Def00EA
S _PSW Def00D0
S _IPINSENS1 Def00E6
S _DEVCLKCFG1 Def00F2
S _P3PINCFG Def00FC
S __sdcc_gsinit_startup Ref0000
S G$FRAMCFG1$0$0 Def00DC
S G$SPISIZE$0$0 Def00C3
S G$INTPRI1$0$0 Def00E2
S G$DPS$0$0 Def0086
S _IPINSENS2 Def00E7
S _DEVCLKCFG2 Def00F3
S _P4PINCFG Def00FD
S G$FRAMCFG2$0$0 Def00DD
S G$INTPRI2$0$0 Def00E3
S _P5PINCFG Def00FE
S _UART0CFG Def00A2
S _P6PINCFG Def00FF
S _UART1CFG Def00B1
S G$MPAGE$0$0 Def00F1
S __mcs51_genXRAMCLEAR Ref0000
S G$USERFLAGS$0$0 Def00F8
S G$PERIPHEN1$0$0 Def00F4
S G$TH0$0$0 Def008B
S _P0 Def0080
A _CODE size 0 flags 0
A RSEG size 0 flags 0
A REG_BANK_0 size 8 flags 4
A DSEG size 2 flags 0
S _framptr Def0000
S G$framptr$0$0 Def0000
A OSEG size 0 flags 4
A SSEG size 1 flags 0
S __start__stack Def0000
A ISEG size 5 flags 0
S _main_framread_1_1 Def0004
S Lmain$count$1$1 Def0000
S Lmain$cptr$1$1 Def0002
S Lmain$framread$1$1 Def0004
S _main_count_1_1 Def0000
S _main_cptr_1_1 Def0002
A BSEG size 0 flags 80
A PSEG size 0 flags 50
A XSEG size 0 flags 40
A XISEG size 0 flags 40
A CSEG size 40 flags 20
S _main Def0008
S A$V3K_FRAM_Watch_SDCC$601 Def003D
S A$V3K_FRAM_Watch_SDCC$511 Def0003
S A$V3K_FRAM_Watch_SDCC$540 Def000A
S A$V3K_FRAM_Watch_SDCC$513 Def0006
S A$V3K_FRAM_Watch_SDCC$550 Def0012
S A$V3K_FRAM_Watch_SDCC$541 Def000B
S A$V3K_FRAM_Watch_SDCC$605 Def003F
S A$V3K_FRAM_Watch_SDCC$560 Def0018
S A$V3K_FRAM_Watch_SDCC$551 Def0013
S A$V3K_FRAM_Watch_SDCC$542 Def000C
S A$V3K_FRAM_Watch_SDCC$543 Def000D
S XG$main$0$0 Def003F
S A$V3K_FRAM_Watch_SDCC$580 Def002E
S A$V3K_FRAM_Watch_SDCC$590 Def0038
S A$V3K_FRAM_Watch_SDCC$581 Def002F
S A$V3K_FRAM_Watch_SDCC$591 Def0039
S A$V3K_FRAM_Watch_SDCC$555 Def0014
S A$V3K_FRAM_Watch_SDCC$592 Def003A
S A$V3K_FRAM_Watch_SDCC$583 Def0031
S A$V3K_FRAM_Watch_SDCC$565 Def001B
S A$V3K_FRAM_Watch_SDCC$556 Def0016
S A$V3K_FRAM_Watch_SDCC$547 Def000E
S C$V3K_FRAM_Watch_SDCC.c$40$1$0 Def0014
S A$V3K_FRAM_Watch_SDCC$575 Def0024
S A$V3K_FRAM_Watch_SDCC$566 Def001E
S A$V3K_FRAM_Watch_SDCC$548 Def0010
S A$V3K_FRAM_Watch_SDCC$539 Def0008
S A$V3K_FRAM_Watch_SDCC$585 Def0033
S A$V3K_FRAM_Watch_SDCC$576 Def0027
S A$V3K_FRAM_Watch_SDCC$567 Def0020
S A$V3K_FRAM_Watch_SDCC$549 Def0011
S A$V3K_FRAM_Watch_SDCC$586 Def0035
S A$V3K_FRAM_Watch_SDCC$568 Def0022
S C$V3K_FRAM_Watch_SDCC.c$42$1$1 Def0018
S A$V3K_FRAM_Watch_SDCC$596 Def003B
S A$V3K_FRAM_Watch_SDCC$587 Def0036
S A$V3K_FRAM_Watch_SDCC$578 Def002A
S A$V3K_FRAM_Watch_SDCC$479 Def0000
S C$V3K_FRAM_Watch_SDCC.c$52$1$1 Def003F
S C$V3K_FRAM_Watch_SDCC.c$43$1$1 Def001B
S G$main$0$0 Def0008
S A$V3K_FRAM_Watch_SDCC$597 Def003C
S A$V3K_FRAM_Watch_SDCC$579 Def002C
S C$V3K_FRAM_Watch_SDCC.c$37$0$0 Def0008
S A$V3K_FRAM_Watch_SDCC$589 Def0037
S C$V3K_FRAM_Watch_SDCC.c$45$1$1 Def0024
S C$V3K_FRAM_Watch_SDCC.c$38$1$0 Def0008
S C$V3K_FRAM_Watch_SDCC.c$39$1$0 Def000E
S C$V3K_FRAM_Watch_SDCC.c$48$1$1 Def003D
S C$V3K_FRAM_Watch_SDCC.c$46$2$2 Def0024
S __sdcc_program_startup Def0003
A GSINIT0 size 0 flags 20
A GSINIT1 size 0 flags 20
A GSINIT2 size 0 flags 20
A GSINIT3 size 0 flags 20
A GSINIT4 size 0 flags 20
A GSINIT5 size 0 flags 20
A GSINIT size 6 flags 20
S C$V3K_FRAM_Watch_SDCC.c$31$1$1 Def0000
S A$V3K_FRAM_Watch_SDCC$497 Def0000
S A$V3K_FRAM_Watch_SDCC$498 Def0003
A GSFINAL size 3 flags 20
S A$V3K_FRAM_Watch_SDCC$500 Def0000
A HOME size 0 flags 20
A XINIT size 0 flags 20
T 00 00
R 00 00 00 02
T 00 00
R 00 00 00 03
T 00 00
R 00 00 00 03
T 00 00
R 00 00 00 05
T 00 00
R 00 00 00 05
T 00 00
R 00 00 00 06
T 00 00
R 00 00 00 06
T 00 02
R 00 00 00 06
T 00 02
R 00 00 00 06
T 00 04
R 00 00 00 06
T 00 04
R 00 00 00 06
T 00 00
R 00 00 00 0B
T 00 00 02 00 00
R 00 00 00 0B 02 03 00 F6
T 00 00 75 00 00 00 75 00 01 80
R 00 00 00 12 29 03 00 03 29 07 00 03
T 00 00 02 00 03
R 00 00 00 13 00 03 00 0B
T 00 03
R 00 00 00 0B
T 00 03 12 00 08 80 FE
R 00 00 00 0B 00 03 00 0B
T 00 08
R 00 00 00 0B
T 00 08 78 00 00 E4 F6 08 F6 78 00 02 E4 F6 08 F6
R 00 00 00 0B 09 03 00 06 09 0A 00 06
T 00 14 78 00 04 76 00 43 F6 C0 75 00 00 00 74 80
R 00 00 00 0B 09 03 00 06 29 0B 00 03
T 00 20 24 01 F5 00 01
R 00 00 00 0B 29 05 00 03
T 00 24
R 00 00 00 0B
T 00 24 85 00 00 82 85 00 01 83 78
R 00 00 00 0B 29 03 00 03 29 07 00 03
T 00 2B 00 00 86 02 08 86 03 78 00 00 74 01 26 F6
R 00 00 00 0B 09 02 00 06 09 0A 00 06
T 00 37 E4 08 36 F6 EA F0 80 E5
R 00 00 00 0B
T 00 3F
R 00 00 00 0B
T 00 3F 22
R 00 00 00 0B