📄 v3k_fram_watch_sdcc.asm
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;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.5.0-pre1 #1018 (May 7 2005)
; This file generated Thu Mar 29 11:00:52 2007
;--------------------------------------------------------
.module V3K_FRAM_Watch_SDCC
.optsdcc -mmcs51 --model-small
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _main
.globl _AUPREV3
.globl _AUPREV2
.globl _AUPREV1
.globl _AUPREV0
.globl _AUCONFIG2
.globl _AUCONFIG1
.globl _AUSHIFTCFG
.globl _AURES3
.globl _AURES2
.globl _AURES1
.globl _AURES0
.globl _AUB1
.globl _AUB0
.globl _AUB0DIV
.globl _AUC3
.globl _AUC2
.globl _AUC1
.globl _AUC0
.globl _AUA1
.globl _AUA0
.globl _FRAMCFG2
.globl _FRAMCFG1
.globl _I2CRXTX
.globl _I2CSTATUS
.globl _I2CIDCFG
.globl _I2CTIMING
.globl _I2CCONFIG
.globl _SPISTATUS
.globl _SPIRXTX3
.globl _SPIRXTX2
.globl _SPIRXTX1
.globl _SPIRXTX0
.globl _SPISIZE
.globl _SPICONFIG
.globl _SPICTRL
.globl _UART1EXT
.globl _UART1BRH
.globl _UART1BRL
.globl _UART1BUF
.globl _UART1CFG
.globl _UART1INT
.globl _PWMCLKCFG
.globl _PWMTMRF
.globl _PWMTMREN
.globl _PWMDATA
.globl _PWMLDPOL
.globl _PWMEN
.globl _PWMCFG
.globl _UART0EXT
.globl _UART0BRH
.globl _UART0BRL
.globl _UART0BUF
.globl _UART0CFG
.globl _UART0INT
.globl _PWC1CFG
.globl _PWC0CFG
.globl _P6PINCFG
.globl _P5PINCFG
.globl _P4PINCFG
.globl _P3PINCFG
.globl _P2PINCFG
.globl _P1PINCFG
.globl _P0PINCFG
.globl _USERFLAGS
.globl _PORTINEN
.globl _DEVMEMCFG
.globl _PERIPHEN2
.globl _PERIPHEN1
.globl _DEVCLKCFG2
.globl _DEVCLKCFG1
.globl _MPAGE
.globl _B
.globl _FPICLKSPD
.globl _FPIDATAH
.globl _FPIDATAL
.globl _FPIADDRH
.globl _FPIADDRL
.globl _FPICONFIG
.globl _GENINTEN
.globl _IPINSENS2
.globl _IPINSENS1
.globl _INTSRC2
.globl _INTSRC1
.globl _INTPRI2
.globl _INTPRI1
.globl _DEVIOMAP
.globl _ACC
.globl _XMEMCTRL
.globl _IPINFLAG2
.globl _IPININV2
.globl _IPININV1
.globl _PSW
.globl _P6
.globl _P4
.globl _PORTCHG
.globl _IPINFLAG1
.globl _P3
.globl _INTEN2
.globl _P2
.globl _T2CLKCFG
.globl _T2CON
.globl _T1CON
.globl _T0CON
.globl _T0T1CLKCFG
.globl _P5
.globl _RCAP2H
.globl _RCAP2L
.globl _RCAP1H
.globl _RCAP1L
.globl _RCAP0H
.globl _RCAP0L
.globl _WDTCFG
.globl _P1
.globl _TH2
.globl _TL2
.globl _TH1
.globl _TL1
.globl _TH0
.globl _TL0
.globl _T0T1CFG
.globl _INTEN1
.globl _PCON
.globl _DPS
.globl _DPH1
.globl _DPL1
.globl _DPH0
.globl _DPL0
.globl _SP
.globl _P0
.globl __XPAGE
.globl _frambase
.globl _framptr
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
.area RSEG (DATA)
G$_XPAGE$0$0 == 0x00f1
__XPAGE = 0x00f1
G$P0$0$0 == 0x0080
_P0 = 0x0080
G$SP$0$0 == 0x0081
_SP = 0x0081
G$DPL0$0$0 == 0x0082
_DPL0 = 0x0082
G$DPH0$0$0 == 0x0083
_DPH0 = 0x0083
G$DPL1$0$0 == 0x0084
_DPL1 = 0x0084
G$DPH1$0$0 == 0x0085
_DPH1 = 0x0085
G$DPS$0$0 == 0x0086
_DPS = 0x0086
G$PCON$0$0 == 0x0087
_PCON = 0x0087
G$INTEN1$0$0 == 0x0088
_INTEN1 = 0x0088
G$T0T1CFG$0$0 == 0x0089
_T0T1CFG = 0x0089
G$TL0$0$0 == 0x008a
_TL0 = 0x008a
G$TH0$0$0 == 0x008b
_TH0 = 0x008b
G$TL1$0$0 == 0x008c
_TL1 = 0x008c
G$TH1$0$0 == 0x008d
_TH1 = 0x008d
G$TL2$0$0 == 0x008e
_TL2 = 0x008e
G$TH2$0$0 == 0x008f
_TH2 = 0x008f
G$P1$0$0 == 0x0090
_P1 = 0x0090
G$WDTCFG$0$0 == 0x0091
_WDTCFG = 0x0091
G$RCAP0L$0$0 == 0x0092
_RCAP0L = 0x0092
G$RCAP0H$0$0 == 0x0093
_RCAP0H = 0x0093
G$RCAP1L$0$0 == 0x0094
_RCAP1L = 0x0094
G$RCAP1H$0$0 == 0x0095
_RCAP1H = 0x0095
G$RCAP2L$0$0 == 0x0096
_RCAP2L = 0x0096
G$RCAP2H$0$0 == 0x0097
_RCAP2H = 0x0097
G$P5$0$0 == 0x0098
_P5 = 0x0098
G$T0T1CLKCFG$0$0 == 0x0099
_T0T1CLKCFG = 0x0099
G$T0CON$0$0 == 0x009a
_T0CON = 0x009a
G$T1CON$0$0 == 0x009b
_T1CON = 0x009b
G$T2CON$0$0 == 0x009c
_T2CON = 0x009c
G$T2CLKCFG$0$0 == 0x009d
_T2CLKCFG = 0x009d
G$P2$0$0 == 0x00a0
_P2 = 0x00a0
G$INTEN2$0$0 == 0x00a8
_INTEN2 = 0x00a8
G$P3$0$0 == 0x00b0
_P3 = 0x00b0
G$IPINFLAG1$0$0 == 0x00b8
_IPINFLAG1 = 0x00b8
G$PORTCHG$0$0 == 0x00b9
_PORTCHG = 0x00b9
G$P4$0$0 == 0x00c0
_P4 = 0x00c0
G$P6$0$0 == 0x00c8
_P6 = 0x00c8
G$PSW$0$0 == 0x00d0
_PSW = 0x00d0
G$IPININV1$0$0 == 0x00d6
_IPININV1 = 0x00d6
G$IPININV2$0$0 == 0x00d7
_IPININV2 = 0x00d7
G$IPINFLAG2$0$0 == 0x00d8
_IPINFLAG2 = 0x00d8
G$XMEMCTRL$0$0 == 0x00d9
_XMEMCTRL = 0x00d9
G$ACC$0$0 == 0x00e0
_ACC = 0x00e0
G$DEVIOMAP$0$0 == 0x00e1
_DEVIOMAP = 0x00e1
G$INTPRI1$0$0 == 0x00e2
_INTPRI1 = 0x00e2
G$INTPRI2$0$0 == 0x00e3
_INTPRI2 = 0x00e3
G$INTSRC1$0$0 == 0x00e4
_INTSRC1 = 0x00e4
G$INTSRC2$0$0 == 0x00e5
_INTSRC2 = 0x00e5
G$IPINSENS1$0$0 == 0x00e6
_IPINSENS1 = 0x00e6
G$IPINSENS2$0$0 == 0x00e7
_IPINSENS2 = 0x00e7
G$GENINTEN$0$0 == 0x00e8
_GENINTEN = 0x00e8
G$FPICONFIG$0$0 == 0x00e9
_FPICONFIG = 0x00e9
G$FPIADDRL$0$0 == 0x00ea
_FPIADDRL = 0x00ea
G$FPIADDRH$0$0 == 0x00eb
_FPIADDRH = 0x00eb
G$FPIDATAL$0$0 == 0x00ec
_FPIDATAL = 0x00ec
G$FPIDATAH$0$0 == 0x00ed
_FPIDATAH = 0x00ed
G$FPICLKSPD$0$0 == 0x00ee
_FPICLKSPD = 0x00ee
G$B$0$0 == 0x00f0
_B = 0x00f0
G$MPAGE$0$0 == 0x00f1
_MPAGE = 0x00f1
G$DEVCLKCFG1$0$0 == 0x00f2
_DEVCLKCFG1 = 0x00f2
G$DEVCLKCFG2$0$0 == 0x00f3
_DEVCLKCFG2 = 0x00f3
G$PERIPHEN1$0$0 == 0x00f4
_PERIPHEN1 = 0x00f4
G$PERIPHEN2$0$0 == 0x00f5
_PERIPHEN2 = 0x00f5
G$DEVMEMCFG$0$0 == 0x00f6
_DEVMEMCFG = 0x00f6
G$PORTINEN$0$0 == 0x00f7
_PORTINEN = 0x00f7
G$USERFLAGS$0$0 == 0x00f8
_USERFLAGS = 0x00f8
G$P0PINCFG$0$0 == 0x00f9
_P0PINCFG = 0x00f9
G$P1PINCFG$0$0 == 0x00fa
_P1PINCFG = 0x00fa
G$P2PINCFG$0$0 == 0x00fb
_P2PINCFG = 0x00fb
G$P3PINCFG$0$0 == 0x00fc
_P3PINCFG = 0x00fc
G$P4PINCFG$0$0 == 0x00fd
_P4PINCFG = 0x00fd
G$P5PINCFG$0$0 == 0x00fe
_P5PINCFG = 0x00fe
G$P6PINCFG$0$0 == 0x00ff
_P6PINCFG = 0x00ff
G$PWC0CFG$0$0 == 0x009e
_PWC0CFG = 0x009e
G$PWC1CFG$0$0 == 0x009f
_PWC1CFG = 0x009f
G$UART0INT$0$0 == 0x00a1
_UART0INT = 0x00a1
G$UART0CFG$0$0 == 0x00a2
_UART0CFG = 0x00a2
G$UART0BUF$0$0 == 0x00a3
_UART0BUF = 0x00a3
G$UART0BRL$0$0 == 0x00a4
_UART0BRL = 0x00a4
G$UART0BRH$0$0 == 0x00a5
_UART0BRH = 0x00a5
G$UART0EXT$0$0 == 0x00a6
_UART0EXT = 0x00a6
G$PWMCFG$0$0 == 0x00a9
_PWMCFG = 0x00a9
G$PWMEN$0$0 == 0x00aa
_PWMEN = 0x00aa
G$PWMLDPOL$0$0 == 0x00ab
_PWMLDPOL = 0x00ab
G$PWMDATA$0$0 == 0x00ac
_PWMDATA = 0x00ac
G$PWMTMREN$0$0 == 0x00ad
_PWMTMREN = 0x00ad
G$PWMTMRF$0$0 == 0x00ae
_PWMTMRF = 0x00ae
G$PWMCLKCFG$0$0 == 0x00af
_PWMCLKCFG = 0x00af
G$UART1INT$0$0 == 0x00b0
_UART1INT = 0x00b0
G$UART1CFG$0$0 == 0x00b1
_UART1CFG = 0x00b1
G$UART1BUF$0$0 == 0x00b2
_UART1BUF = 0x00b2
G$UART1BRL$0$0 == 0x00b3
_UART1BRL = 0x00b3
G$UART1BRH$0$0 == 0x00b4
_UART1BRH = 0x00b4
G$UART1EXT$0$0 == 0x00b5
_UART1EXT = 0x00b5
G$SPICTRL$0$0 == 0x00c1
_SPICTRL = 0x00c1
G$SPICONFIG$0$0 == 0x00c2
_SPICONFIG = 0x00c2
G$SPISIZE$0$0 == 0x00c3
_SPISIZE = 0x00c3
G$SPIRXTX0$0$0 == 0x00c4
_SPIRXTX0 = 0x00c4
G$SPIRXTX1$0$0 == 0x00c5
_SPIRXTX1 = 0x00c5
G$SPIRXTX2$0$0 == 0x00c6
_SPIRXTX2 = 0x00c6
G$SPIRXTX3$0$0 == 0x00c7
_SPIRXTX3 = 0x00c7
G$SPISTATUS$0$0 == 0x00c9
_SPISTATUS = 0x00c9
G$I2CCONFIG$0$0 == 0x00d1
_I2CCONFIG = 0x00d1
G$I2CTIMING$0$0 == 0x00d2
_I2CTIMING = 0x00d2
G$I2CIDCFG$0$0 == 0x00d3
_I2CIDCFG = 0x00d3
G$I2CSTATUS$0$0 == 0x00d4
_I2CSTATUS = 0x00d4
G$I2CRXTX$0$0 == 0x00d5
_I2CRXTX = 0x00d5
G$FRAMCFG1$0$0 == 0x00dc
_FRAMCFG1 = 0x00dc
G$FRAMCFG2$0$0 == 0x00dd
_FRAMCFG2 = 0x00dd
G$AUA0$0$0 == 0x00a2
_AUA0 = 0x00a2
G$AUA1$0$0 == 0x00a3
_AUA1 = 0x00a3
G$AUC0$0$0 == 0x00a4
_AUC0 = 0x00a4
G$AUC1$0$0 == 0x00a5
_AUC1 = 0x00a5
G$AUC2$0$0 == 0x00a6
_AUC2 = 0x00a6
G$AUC3$0$0 == 0x00a7
_AUC3 = 0x00a7
G$AUB0DIV$0$0 == 0x00b1
_AUB0DIV = 0x00b1
G$AUB0$0$0 == 0x00b2
_AUB0 = 0x00b2
G$AUB1$0$0 == 0x00b3
_AUB1 = 0x00b3
G$AURES0$0$0 == 0x00b4
_AURES0 = 0x00b4
G$AURES1$0$0 == 0x00b5
_AURES1 = 0x00b5
G$AURES2$0$0 == 0x00b6
_AURES2 = 0x00b6
G$AURES3$0$0 == 0x00b7
_AURES3 = 0x00b7
G$AUSHIFTCFG$0$0 == 0x00c1
_AUSHIFTCFG = 0x00c1
G$AUCONFIG1$0$0 == 0x00c2
_AUCONFIG1 = 0x00c2
G$AUCONFIG2$0$0 == 0x00c3
_AUCONFIG2 = 0x00c3
G$AUPREV0$0$0 == 0x00c4
_AUPREV0 = 0x00c4
G$AUPREV1$0$0 == 0x00c5
_AUPREV1 = 0x00c5
G$AUPREV2$0$0 == 0x00c6
_AUPREV2 = 0x00c6
G$AUPREV3$0$0 == 0x00c7
_AUPREV3 = 0x00c7
;--------------------------------------------------------
; special function bits
;--------------------------------------------------------
.area RSEG (DATA)
;--------------------------------------------------------
; overlayable register banks
;--------------------------------------------------------
.area REG_BANK_0 (REL,OVR,DATA)
.ds 8
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
.area DSEG (DATA)
G$framptr$0$0==.
_framptr::
.ds 2
;--------------------------------------------------------
; overlayable items in internal ram
;--------------------------------------------------------
.area OSEG (OVR,DATA)
;--------------------------------------------------------
; Stack segment in internal ram
;--------------------------------------------------------
.area SSEG (DATA)
__start__stack:
.ds 1
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
.area ISEG (DATA)
Lmain$count$1$1==.
_main_count_1_1::
.ds 2
Lmain$cptr$1$1==.
_main_cptr_1_1::
.ds 2
Lmain$framread$1$1==.
_main_framread_1_1::
.ds 1
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
.area BSEG (BIT)
;--------------------------------------------------------
; paged external ram data
;--------------------------------------------------------
.area PSEG (PAG,XDATA)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
.area XSEG (XDATA)
G$frambase$0$0 == 0x8000
_frambase = 0x8000
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
.area XISEG (XDATA)
.area CSEG (CODE)
.area GSINIT0 (CODE)
.area GSINIT1 (CODE)
.area GSINIT2 (CODE)
.area GSINIT3 (CODE)
.area GSINIT4 (CODE)
.area GSINIT5 (CODE)
;--------------------------------------------------------
; interrupt vector
;--------------------------------------------------------
.area CSEG (CODE)
__interrupt_vect:
ljmp __sdcc_gsinit_startup
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area CSEG (CODE)
.area GSINIT (CODE)
.area GSFINAL (CODE)
.area GSINIT (CODE)
.globl __sdcc_gsinit_startup
.globl __sdcc_program_startup
.globl __start__stack
.globl __mcs51_genXINIT
.globl __mcs51_genXRAMCLEAR
.globl __mcs51_genRAMCLEAR
G$main$0$0 ==.
C$V3K_FRAM_Watch_SDCC.c$31$1$1 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:31: xdata unsigned char * data framptr = &frambase ; //Init a pointer in IRAM pointing to the frambase var.
; genAddrOf
mov _framptr,#_frambase
mov (_framptr + 1),#(_frambase >> 8)
.area GSFINAL (CODE)
ljmp __sdcc_program_startup
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME (CODE)
.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CSEG (CODE)
__sdcc_program_startup:
lcall _main
; return from main will lock up
sjmp .
;------------------------------------------------------------
;Allocation info for local variables in function 'main'
;------------------------------------------------------------
;count Allocated with name '_main_count_1_1'
;cptr Allocated with name '_main_cptr_1_1'
;framread Allocated with name '_main_framread_1_1'
;------------------------------------------------------------
G$main$0$0 ==.
C$V3K_FRAM_Watch_SDCC.c$37$0$0 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:37: void main (void){
; -----------------------------------------
; function main
; -----------------------------------------
_main:
ar2 = 0x02
ar3 = 0x03
ar4 = 0x04
ar5 = 0x05
ar6 = 0x06
ar7 = 0x07
ar0 = 0x00
ar1 = 0x01
C$V3K_FRAM_Watch_SDCC.c$38$1$0 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:38: volatile idata count = 0x00; //general purpose counter
; genAssign
mov r0,#_main_count_1_1
clr a
mov @r0,a
inc r0
mov @r0,a
C$V3K_FRAM_Watch_SDCC.c$39$1$0 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:39: volatile idata int cptr= 0x00; //general purpose counter
; genAssign
mov r0,#_main_cptr_1_1
clr a
mov @r0,a
inc r0
mov @r0,a
C$V3K_FRAM_Watch_SDCC.c$40$1$0 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:40: volatile idata char framread = 0x00;
; genAssign
mov r0,#_main_framread_1_1
mov @r0,#0x00
C$V3K_FRAM_Watch_SDCC.c$42$1$1 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:42: DEVMEMCFG |= 0xC0; //Activate the FRAM memory
; genOr
orl _DEVMEMCFG,#0xC0
C$V3K_FRAM_Watch_SDCC.c$43$1$1 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:43: framptr = (&frambase + 0x100);
; genPlus
; genPlus aligned array
mov _framptr,#0x00
mov a,#(_frambase >> 8)
add a,#0x01
mov (_framptr + 1),a
C$V3K_FRAM_Watch_SDCC.c$45$1$1 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:45: do{
00101$:
C$V3K_FRAM_Watch_SDCC.c$46$2$2 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:46: *framptr = count++;
; genAssign
mov dpl,_framptr
mov dph,(_framptr + 1)
; genAssign
mov r0,#_main_count_1_1
mov ar2,@r0
inc r0
mov ar3,@r0
; genPlus
mov r0,#_main_count_1_1
; genPlusIncr
mov a,#0x01
add a,@r0
mov @r0,a
; Peephole 181 changed mov to clr
clr a
inc r0
addc a,@r0
mov @r0,a
; genCast
; genPointerSet
; genFarPointerSet
mov a,r2
movx @dptr,a
C$V3K_FRAM_Watch_SDCC.c$48$1$1 ==.
;c:/APP_ENG/Released_Demo_Programs/V3k_demo_programs/V3K_FRAM_Watch_SDCC/V3K_FRAM_Watch_SDCC.c:48: }while(1);
; Peephole 112.b changed ljmp to sjmp
sjmp 00101$
00104$:
C$V3K_FRAM_Watch_SDCC.c$52$1$1 ==.
XG$main$0$0 ==.
ret
.area CSEG (CODE)
.area XINIT (CODE)
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