dac_test.mdl

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      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      Interpolate	      on
    }
    Block {
      BlockType		      Math
      Operator		      "exp"
      OutputSignalType	      "auto"
      SampleTime	      "-1"
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
    }
    Block {
      BlockType		      "M-S-Function"
      MFile		      "mlfile"
    }
    Block {
      BlockType		      Mux
      Inputs		      "4"
      DisplayOption	      "none"
      BusObject		      "BusObject"
      NonVirtualBus	      off
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      Product
      Inputs		      "2"
      Multiplication	      "Element-wise(.*)"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Zero"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      RelationalOperator
      Operator		      ">="
      InputSameDT	      on
      LogicOutDataTypeMode    "Logical (see Configuration Parameters: Optimiza"
"tion)"
      LogicDataType	      "uint(8)"
      ZeroCross		      on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Scope
      Floating		      off
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "0"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
    }
    Block {
      BlockType		      Sin
      SineType		      "Time based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Bias		      "0"
      Frequency		      "1"
      Phase		      "0"
      Samples		      "10"
      Offset		      "0"
      SampleTime	      "-1"
      VectorParams1D	      on
    }
    Block {
      BlockType		      StateSpace
      A			      "1"
      B			      "1"
      C			      "1"
      D			      "1"
      X0		      "0"
      AbsoluteTolerance	      "auto"
      Realization	      "auto"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Terminator
    }
    Block {
      BlockType		      TransferFcn
      Numerator		      "[1]"
      Denominator	      "[1 2 1]"
      AbsoluteTolerance	      "auto"
      Realization	      "auto"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "dac_test"
    Location		    [2, 70, 1022, 720]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    124
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    ZoomFactor		    "74"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      " System Generator"
      Tag		      "genX"
      Ports		      []
      Position		      [526, 777, 583, 834]
      ShowName		      off
      AttributesFormatString  "System\\nGenerator"
      UserDataPersistent      on
      UserData		      "DataTag0"
      SourceBlock	      "xbsIndex_r3/ System Generator"
      SourceType	      "Xilinx System Generator"
      ShowPortLabels	      on
      xilinxfamily	      "Spartan2"
      part		      "xc2s15"
      speed		      "-6"
      package		      "cs144"
      synthesis_tool	      "XST"
      directory		      "./sysgenADCDACysgen"
      testbench		      on
      simulink_period	      "1"
      sysclk_period	      "6.8"
      incr_netlist	      off
      trim_vbits	      "Everywhere in SubSystem"
      dbl_ovrd		      "According to Block Masks"
      core_generation	      "According to Block Masks"
      run_coregen	      off
      deprecated_control      off
      eval_field	      "0"
    }
    Block {
      BlockType		      SubSystem
      Name		      "(c) Copyright 1995-2004 Xilinx, Inc.\n#-- All r"
"ights reserved."
      Ports		      []
      Position		      [300, 751, 425, 829]
      DropShadow	      on
      FontName		      "Arial"
      FontSize		      12
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskDisplay	      "disp('Double click \\nfor\\nCopyright Notice.')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"(c) Copyright 1995-2004 Xilinx, Inc.\n#-- All"
" rights reserved."
	Location		[214, 74, 1022, 724]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Annotation {
	  Name			  "Copyright(C) 2004 by  Xilinx, Inc. All righ"
"ts reserved.\n\nThis file contains proprietary, confidential information of X"
"ilinx, Inc., is distributed under license\nfrom Xilinx, Inc., and may be used"
", copied and/or disclosed only pursuant to the terms of a valid license\nagre"
"ement with Xilinx, Inc. Xilinx hereby grants you a license to use this file s"
"olely for design,\nsimulation, implementation and creation of design files li"
"mited to Xilinx devices or technologies. Use \nwith non-Xilinx devices or tec"
"hnologies is expressly prohibited and immediately terminates your license \nu"
"nless covered by a separate agreement.\n\nXilinx is providing this design, co"
"de, or information \"as-is\" solely for use in developing programs and \nsolu"
"tions for Xilinx devices, with no obligation on the part of Xilinx to provide"
" support. By providing\nthis design, code, or information as one possible imp"
"lementation of this feature, application or standard,\nXilinx is making no re"
"presentation that this implementation is free from any claims of infringement"
". You\nare responsible for obtaining any rights you may require for your impl"
"ementation. Xilinx expressly disclaims\nany warranty whatsoever with respect "
"to the adequacy of the implementation, including but not limited to any\nwarr"
"anties or representations that this implementation is free from claims of inf"
"ringement, implied warranties\nof merchantability or fitness for a particular"
" purpose.\n\nXilinx products are not intended for use in life support applian"
"ces, devices, or systems. Use in such \napplications is expressly prohibited."
"\n\nAny modifications that are made to the Source Code are done at the user's"
" sole risk and will be unsupported. \n\nThis copyright and support notice mus"
"t be retained as part of this text at all times. \n(c) Copyright 1995-2004 Xi"
"linx, Inc. All rights reserved."
	  Position		  [6, 192]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  12
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "ADC\n(XAPP155)"
      Ports		      [1, 4]
      Position		      [460, 329, 560, 436]
      BackgroundColor	      "lightBlue"
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      System {
	Name			"ADC\n(XAPP155)"
	Location		[2, 75, 997, 724]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "AgtR"
	  Position		  [35, 13, 65, 27]
	  ShowName		  off
	  Port			  "1"
	  IconDisplay		  "Port number and signal name"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "'c1'"
	  Ports			  [0, 1]
	  Position		  [60, 391, 100, 409]
	  SourceBlock		  "xbsIndex_r3/Constant"
	  SourceType		  "Xilinx Constant Block"
	  const			  "0"
	  equ			  "P=C"
	  arith_type		  "Unsigned"
	  n_bits		  "4"
	  bin_pt		  "0"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  iostate		  "0"
	  explicit_period	  off
	  period		  "1"
	  dbl_ovrd		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "ADCOut \nRegister"
	  Ports			  [2, 1]
	  Position		  [370, 141, 430, 234]
	  SourceBlock		  "xbsIndex_r3/Register"
	  SourceType		  "Xilinx Register Block"
	  init			  "0"
	  reg_only_valid	  off
	  explicit_period	  off
	  period		  "1"
	  rst			  off
	  en			  on
	  out_en		  off
	  dbl_ovrd		  off
	  show_param		  off
	  xl_area		  "[7 14 0 0 0 0 0]"
	  xl_use_area		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [225, 561, 265, 579]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r3/Constant"
	  SourceType		  "Xilinx Constant Block"
	  const			  "0"
	  equ			  "P=C"
	  arith_type		  "Unsigned"
	  n_bits		  "14"
	  bin_pt		  "0"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  iostate		  "0"
	  explicit_period	  off
	  period		  "1"
	  dbl_ovrd		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  Ports			  [0, 1]
	  Position		  [210, 426, 250, 444]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r3/Constant"
	  SourceType		  "Xilinx Constant Block"
	  const			  "0"
	  equ			  "P=C"
	  arith_type		  "Unsigned"
	  n_bits		  "1"
	  bin_pt		  "0"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  iostate		  "0"
	  explicit_period	  off
	  period		  "1"
	  dbl_ovrd		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "DAC Out"
	  Ports			  [1, 1]
	  Position		  [625, 173, 655, 187]
	  SourceBlock		  "xbsIndex_r3/Gateway Out"
	  SourceType		  "Xilinx Gateway Out"
	  output_type		  "Double"
	  nbits			  "8"
	  bin_pt		  "6"
	  arith_type		  "Boolean"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  hdl_port		  on
	  timing_constraint	  "Data Rate;  Set 'FAST' Attribute"
	  locs_specified	  off
	  LOCs			  "{}"
	  needs_fixed_name	  off
	  show_param		  off
	  xl_area		  "[0 0 0 0 1 0 0]"
	  xl_use_area		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "DAC Out1"
	  Ports			  [1, 1]
	  Position		  [620, 33, 650, 47]
	  SourceBlock		  "xbsIndex_r3/Gateway Out"
	  SourceType		  "Xilinx Gateway Out"
	  output_type		  "Double"
	  nbits			  "8"
	  bin_pt		  "6"
	  arith_type		  "Boolean"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  hdl_port		  on
	  timing_constraint	  "Data Rate;  Set 'FAST' Attribute"
	  locs_specified	  off
	  LOCs			  "{}"
	  needs_fixed_name	  off
	  show_param		  off
	  xl_area		  "[0 0 0 0 1 0 0]"
	  xl_use_area		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "DAC Out2"
	  Ports			  [1, 1]
	  Position		  [625, 68, 655, 82]
	  SourceBlock		  "xbsIndex_r3/Gateway Out"
	  SourceType		  "Xilinx Gateway Out"
	  output_type		  "Double"
	  nbits			  "8"
	  bin_pt		  "6"
	  arith_type		  "Boolean"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  hdl_port		  on
	  timing_constraint	  "Data Rate;  Set 'FAST' Attribute"
	  locs_specified	  off
	  LOCs			  "{}"
	  needs_fixed_name	  off
	  show_param		  off
	  xl_area		  "[0 0 0 0 1 0 0]"
	  xl_use_area		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "DAC Out3"
	  Ports			  [1, 1]
	  Position		  [625, 103, 655, 117]
	  SourceBlock		  "xbsIndex_r3/Gateway Out"
	  SourceType		  "Xilinx Gateway Out"
	  output_type		  "Double"
	  nbits			  "8"
	  bin_pt		  "6"
	  arith_type		  "Boolean"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  hdl_port		  on
	  timing_constraint	  "Data Rate;  Set 'FAST' Attribute"
	  locs_specified	  off
	  LOCs			  "{}"
	  needs_fixed_name	  off
	  show_param		  off
	  xl_area		  "[0 0 0 0 1 0 0]"
	  xl_use_area		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "DAC Out4"
	  Ports			  [1, 1]
	  Position		  [625, 138, 655, 152]
	  SourceBlock		  "xbsIndex_r3/Gateway Out"
	  SourceType		  "Xilinx Gateway Out"
	  output_type		  "Double"
	  nbits			  "8"
	  bin_pt		  "6"
	  arith_type		  "Boolean"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  hdl_port		  on
	  timing_constraint	  "Data Rate;  Set 'FAST' Attribute"
	  locs_specified	  off
	  LOCs			  "{}"