fir_160_tap.v

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`define  udly 3 
`define  TAP  160

module  fir_160_tap(  
                   din  ,
                   dout ,
                   clk  ,
                   rstn
                   );  

input [11 : 0]  din  ;
output[31 : 0]  dout ;
input         clk  ;
input         rstn ;


//////////////////////////////////

reg[7:0]     count ;
always @(posedge clk or negedge rstn)
if (!rstn )
    count  <= #`udly 8'h00 ;
else if(count == `TAP - 1)
    count  <= #`udly 8'h00 ;    
else 
    count  <= #`udly count + 1'b1 ;      

//===============================
reg  comp_z_1 ;
reg  comp_z_2 ;
reg  comp_z_3 ;
reg  comp_z_4 ;

always @(posedge clk or negedge rstn )
if (!rstn )
    comp_z_1  <= #`udly 1'b0 ;
else if(count == 8'h00)
    comp_z_1  <= #`udly 1'b1 ;
else 
    comp_z_1  <= #`udly 1'b0 ;

always @(posedge clk or negedge rstn )
if (!rstn )
    comp_z_2  <= #`udly 1'b0 ;
else 
    comp_z_2  <= #`udly comp_z_1 ;
        
always @(posedge clk or negedge rstn )
if (!rstn )
    comp_z_3  <= #`udly 1'b0 ;
else 
    comp_z_3  <= #`udly comp_z_2 ;
        
always @(posedge clk or negedge rstn )
if (!rstn )
    comp_z_4  <= #`udly 1'b0 ;
else 
    comp_z_4  <= #`udly comp_z_3 ;

wire    load_en = (count == `TAP - 1);
wire    done_en = comp_z_2 ;
      
//==========================

reg [11:0]  din_z   ;
reg [11:0]  asr_z_1 ;
wire[11:0]  asr_do  ;

always @(posedge clk or negedge rstn)
if (!rstn )
    din_z  <= #`udly 12'h000;
else 
    din_z  <= #`udly din     ;     

fir_asr asr(
           .addr(count[7:0]       ) ,
           .d   (din_z[11:0]      ) ,
           .q   (asr_do           ) ,
           .clk (clk              ) ,
           .en  (load_en          ) ,
           .rstn(rstn             )
           );
           
always @(posedge clk or negedge rstn )
if (!rstn )
    asr_z_1  <= #`udly 12'h000 ;
else 
    asr_z_1  <= #`udly asr_do  ;

//============================
 
reg [11:0]  rom_z_1 ;
wire[11:0]  rom_do  ;                   
fir_rom rom( 
           .clk (clk          ) , 
           .addr(count[7:0]   ) , 
           .dout(rom_do[11:0] ) 
           );
           
always @(posedge clk or negedge rstn )
if (!rstn )
     rom_z_1 <= #`udly 12'h000 ;
else 
     rom_z_1 <= #`udly rom_do  ;
                     
//============================

wire [31:0] mac_dout ;
fir_mac mac(
           .a   (asr_z_1[11:0] ),
           .b   (rom_z_1[11:0] ),
           .q   (mac_dout      ),
           .rst (done_en       ),
           .clk (clk           )
           );

//===========================

reg[31:0]  dout ;
always @(posedge clk or negedge rstn )
if (!rstn )
    dout  <= #`udly 32'h0000_0000 ;
else if(done_en)
    dout  <= #`udly mac_dout[31:0] ;    
        
//////////////////////////////////////////////
endmodule

 
module fir_mac ( a, b, q, rst, clk);
input [11:0]  a ;
input [11:0]  b ;
output[31:0]  q ;  
input         rst ;
input         clk ;

reg [31:0]    q ;

wire[10:0]    a_val   = a[11] ? (~a[10:0] + 1'b1) : a[10:0] ;
wire[10:0]    b_val   = b[11] ? (~b[10:0] + 1'b1) : b[10:0] ;

wire          ab_sig  =  a[11] & ~b[11] |
                        ~a[11] &  b[11] ;
wire[21:0]    ab_val  = a_val * b_val   ;
wire[31:0]    abe     = (ab_val == 22'h000000) ? 32'h0000_0000 : 
                        {{10{ab_sig}}, ab_sig ? (~ab_val[21:0] + 1'b1) : ab_val[21:0]};
wire[31:0]    abr     = abe + q ;

always @(posedge clk) 
if (rst )
     q <= #`udly abe ;
else 
     q <= #`udly abr ;  

endmodule 

   
module fir_asr( addr, d, q, clk, en, rstn ) ;
input [7:0]  addr ;
input [11:0] d    ;
output[11:0] q    ;
input        clk  ;
input        en   ;
input        rstn ;

/////
reg[7:0]     waddr ;
wire         waddr_clear = en & (waddr == `TAP) ;
always @(posedge clk or negedge rstn)
if (!rstn )
    waddr  <= #`udly 8'h00 ;
else if(waddr_clear )
    waddr  <= #`udly 8'h00 ;
else if(en          )
    waddr  <= #`udly waddr + 1'b1 ; 

reg[7:0]     waddr_back ;
always @(posedge clk or negedge rstn )
if (!rstn )
    waddr_back <= #`udly 8'h00 ;
else if(addr == `TAP - 1)
    waddr_back <= #`udly waddr ;

wire[7:0]    raddr = (waddr_back[7:0] > addr[7:0]) ? (waddr_back[7:0] - addr[7:0] - 1   )
                                                   : (waddr_back[7:0] + `TAP - addr[7:0] - 1 ) ; 
          
asr_ram  ram ( 
             .din  (d[11:0]    ),
             .dout (q[11:0]    ),
             .clk  (clk        ),
             .wren (en         ),
             .waddr(waddr[7:0] ),
             .raddr(raddr[7:0] ),
             .oen  (1'b1       )
             );

endmodule

     
module asr_ram (din, dout, clk , wren, waddr, raddr, oen);
input [11:0]  din  ;
output[11:0]  dout ;
input         clk  ;
input         wren ;
input [7:0]   waddr;
input [7:0]   raddr;
input         oen  ;

reg[11:0]     dout ;
reg[11:0]     mem[0:`TAP - 1] ;

integer       i    ;

initial 
begin
   for (i = 0 ; i <`TAP ; i = i + 1 ) 
       mem[i]  = 12'h000 ;
end      

always @(posedge clk )
if (wren )
    mem[waddr] <= #`udly din[11:0] ;

always @(posedge clk )
    dout       <= #`udly mem[raddr] ;
    
endmodule      
      
module fir_rom ( addr, dout, clk);
input [7:0]  addr ;
output[11:0] dout ;
input        clk  ;

reg [11:0]   dout ;
reg [11:0]   data[0:159] ;
initial 
begin
    $readmemh ("rom.txt",data,0,159);
end

always @(posedge clk )
   dout  <= #`udly data[addr] ;

endmodule