iir_6_filter.v

使用ＭＡＴＬＡＢ工具

reg [38:0]  data_add_reg ;
wire[38:0]  data_add     = data_add_reg[38:0] + {{3{data_mul[35]}}, data_mul[35:0]} ;
wire        data_add_clr = iir_add_st ;
wire        data_add_chg = iir_xc0_st | 
                           iir_xc1_st | 
                           iir_xc2_st | 
                           iir_yc2_st | 
                           iir_yc1_st ;
always @(posedge clk or negedge rstn )
if (!rstn )
     data_add_reg  <= #`udly 39'h00_0000_0000 ;
else if(data_add_clr )
     data_add_reg  <= #`udly 39'h00_0000_0000 ;
else if(data_add_chg )
     data_add_reg  <= #`udly data_add[38:0]   ; 
              
/*
reg [35:0]  iir_xc0_mul ,
            iir_xc1_mul ,
            iir_xc2_mul ,
            iir_yc2_mul ,
            iir_yc1_mul ;

always @(posedge clk or negedge rstn )
if     (!rstn       )
        iir_xc0_mul <= #`udly 36'h0_0000_0000 ;
else if(iir_xc0_st  )    
        iir_xc0_mul <= #`udly data_mul[35:0]  ;

always @(posedge clk or negedge rstn )
if     (!rstn       )
        iir_xc1_mul <= #`udly 36'h0_0000_0000 ;
else if(iir_xc1_st  )    
        iir_xc1_mul <= #`udly data_mul[35:0]  ;

always @(posedge clk or negedge rstn )
if     (!rstn       )
        iir_xc2_mul <= #`udly 36'h0_0000_0000 ;
else if(iir_xc2_st  )    
        iir_xc2_mul <= #`udly data_mul[35:0]  ;

always @(posedge clk or negedge rstn )
if     (!rstn       )
        iir_yc2_mul <= #`udly 36'h0_0000_0000 ;
else if(iir_yc2_st  )    
        iir_yc2_mul <= #`udly data_mul[35:0]  ;

always @(posedge clk or negedge rstn )
if     (!rstn       )
        iir_yc1_mul <= #`udly 36'h0_0000_0000 ;
else if(iir_yc1_st  )    
        iir_yc1_mul <= #`udly data_mul[35:0]  ;

wire[35:0]  a_add    = iir_add_st ? iir_xc0_mul[35:0] : 36'h0_0000_0000 ;
wire[35:0]  b_add    = iir_add_st ? iir_xc1_mul[35:0] : 36'h0_0000_0000 ;
wire[35:0]  c_add    = iir_add_st ? iir_xc2_mul[35:0] : 36'h0_0000_0000 ;
wire[35:0]  d_add    = iir_add_st ? iir_yc2_mul[35:0] : 36'h0_0000_0000 ;
wire[35:0]  e_add    = iir_add_st ? iir_yc1_mul[35:0] : 36'h0_0000_0000 ;
wire[38:0]  data_add = a_add + b_add + c_add + d_add + e_add ;
*/
wire        store_y1 = iir_add_st & (tap_cnt == 3'b000) ;
wire        store_y2 = iir_add_st & (tap_cnt == 3'b001) ;
wire        store_y3 = iir_add_st & (tap_cnt == 3'b010) ;
wire        store_y4 = iir_add_st & (tap_cnt == 3'b011) ;
wire        store_y5 = iir_add_st & (tap_cnt == 3'b100) ;
wire        store_y6 = iir_add_st & (tap_cnt == 3'b101) ;

always @(posedge clk or negedge rstn)
if (!rstn )
    y1    <= #`udly 18'h00000 ;
else if(store_y1 )
    y1    <= #`udly data_add_reg[33:16] ;         
                       
always @(posedge clk or negedge rstn)
if (!rstn )
    y2    <= #`udly 18'h00000 ;
else if(store_y2 )
    y2    <= #`udly data_add_reg[33:16] ;         

always @(posedge clk or negedge rstn)
if (!rstn )
    y3    <= #`udly 18'h00000 ;
else if(store_y3 )
    y3    <= #`udly data_add_reg[33:16] ;         

always @(posedge clk or negedge rstn)
if (!rstn )
    y4    <= #`udly 18'h00000 ;
else if(store_y4 )
    y4    <= #`udly data_add_reg[33:16] ;         

always @(posedge clk or negedge rstn)
if (!rstn )
    y5    <= #`udly 18'h00000 ;
else if(store_y5 )
    y5    <= #`udly data_add_reg[33:16] ;         

always @(posedge clk or negedge rstn)
if (!rstn )
    y6    <= #`udly 18'h00000 ;
else if(store_y6 )
    y6    <= #`udly data_add_reg[33:16];         


always @(posedge clk or negedge rstn)
if (!rstn )
begin
    x1    <= #`udly 18'h00000 ;
    x1_z1 <= #`udly 18'h00000 ;
    x1_z2 <= #`udly 18'h00000 ;
end
else if(ce_50k )
begin
    x1    <= #`udly din       ;         
    x1_z1 <= #`udly x1        ;
    x1_z2 <= #`udly x1_z1     ;
end
                       
always @(posedge clk or negedge rstn)
if (!rstn )
begin
    x2    <= #`udly 18'h00000 ;
    x2_z1 <= #`udly 18'h00000 ;
    x2_z2 <= #`udly 18'h00000 ;
end
else if(ce_50k )
begin
    x2    <= #`udly y1        ;         
    x2_z1 <= #`udly x2        ;
    x2_z2 <= #`udly x2_z1     ;
end

always @(posedge clk or negedge rstn)
if (!rstn )
begin
    x3    <= #`udly 18'h00000 ;
    x3_z1 <= #`udly 18'h00000 ;
    x3_z2 <= #`udly 18'h00000 ;
end
else if(ce_50k )
begin
    x3    <= #`udly y2        ;         
    x3_z1 <= #`udly x3        ;
    x3_z2 <= #`udly x3_z1     ;
end

always @(posedge clk or negedge rstn)
if (!rstn )
begin
    x4    <= #`udly 18'h00000 ;
    x4_z1 <= #`udly 18'h00000 ;
    x4_z2 <= #`udly 18'h00000 ;
end
else if(ce_50k )
begin
    x4    <= #`udly y3        ;         
    x4_z1 <= #`udly x4        ;
    x4_z2 <= #`udly x4_z1     ;
end

always @(posedge clk or negedge rstn)
if (!rstn )
begin
    y4_z1 <= #`udly 18'h00000 ;
    y4_z2 <= #`udly 18'h00000 ;
end
else if(ce_50k )
begin
    y4_z1 <= #`udly y4        ;
    y4_z2 <= #`udly y4_z1     ;
end

//=======================================

always @(posedge clk or negedge rstn)
if (!rstn )
begin
    x5    <= #`udly 18'h00000 ;
    x5_z1 <= #`udly 18'h00000 ;
    x5_z2 <= #`udly 18'h00000 ;
end
else if(ce_25k )
begin
    x5    <= #`udly y4_z1     ;         
    x5_z1 <= #`udly x5        ;
    x5_z2 <= #`udly x5_z1     ;
end

always @(posedge clk or negedge rstn)
if (!rstn )
begin
    x6    <= #`udly 18'h00000 ;
    x6_z1 <= #`udly 18'h00000 ;
    x6_z2 <= #`udly 18'h00000 ;
end
else if(ce_25k )
begin
    x6    <= #`udly y5        ;         
    x6_z1 <= #`udly x6        ;
    x6_z2 <= #`udly x6_z1     ;
end

always @(posedge clk or negedge rstn)
if (!rstn )
begin
    y6_z1 <= #`udly 18'h00000 ;
    y6_z2 <= #`udly 18'h00000 ;
end
else if(ce_25k )
begin
    y6_z1 <= #`udly y6        ;
    y6_z2 <= #`udly y6_z1     ;
end

////

wire [17:0]  dout  = fltsel ? y6_z1[17:0] : x5[17:0] ;

///////////////////////////////////////////
endmodule