iir_6_filter.v

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/*
   Module      : iir_6_filter 
   Description : Low Pass Filter(4 IIR) + High Pass Filter(2 IIR)
                 At least 36 Clock Needed.
                 Maximun Sample Rate < 1/(36*clock_period)                  
   Author      : Yu Caogang
   Company     : Beken  
   History     : 2005.9.29  First Version
*/

`define udly 3 

module  iir_6_filter ( 
                      din    ,
                      dout   ,
                      clk    ,
                      fltsel ,
                      ce_50k ,
                      ce_25k ,
                      rstn
                      );

input [17:0]  din     ;  
output[17:0]  dout    ;
input         clk     ;
input         fltsel  ; // Used to select iir_2
input         ce_50k  ;
input         ce_25k  ;
input         rstn    ;

//////////////////////////////////////////////////////
reg [17:0]  x1  , x1_z1, x1_z2,
            x2  , x2_z1, x2_z2,
            x3  , x3_z1, x3_z2,
            x4  , x4_z1, x4_z2,
            x5  , x5_z1, x5_z2,
            x6  , x6_z1, x6_z2;

reg [17:0]  y1  ,
            y2  ,
            y3  ,
            y4  ,
            y5  ,
            y6  ;

reg[2:0]    tap_cnt    ;                  
reg[2:0]    iir_state  ;
reg         iir_2_enable;
wire        iir_xc0_st = (iir_state == 3'b001) ;
wire        iir_xc1_st = (iir_state == 3'b010) ; 
wire        iir_xc2_st = (iir_state == 3'b011) ;
wire        iir_yc2_st = (iir_state == 3'b100) ;
wire        iir_yc1_st = (iir_state == 3'b101) ;
wire        iir_add_st = (iir_state == 3'b110) ;
wire        iir_ext_st = (iir_state == 3'b111) ;
wire        iir_done   = iir_add_st &  iir_2_enable & (tap_cnt == 3'b101) |
                         iir_add_st & !iir_2_enable & (tap_cnt == 3'b011) ;

always @(posedge clk or negedge rstn )
if (!rstn )
     iir_2_enable <= #`udly 1'b0   ;
else if(iir_ext_st )
     iir_2_enable <= #`udly 1'b0   ;
else if(ce_25k )
     iir_2_enable <= #`udly 1'b1   ;

always @(posedge clk or negedge rstn )
if (!rstn )
     iir_state    <= #`udly 3'b000 ;
else 
begin
    case(iir_state[2:0])
    3'b000 :
    if (ce_50k )
        iir_state <= #`udly 3'b001 ;
    else 
        iir_state <= #`udly 3'b000 ;
    3'b001 : // X(n)   * Cx(n)   = XC(n)
        iir_state <= #`udly 3'b010 ;
    3'b010 : // X(n-1) * Cx(n-1) = XC(n-1)
        iir_state <= #`udly 3'b011 ;
    3'b011 : // X(n-2) * Cx(n-2) = XC(n-2)
        iir_state <= #`udly 3'b100 ;        
    3'b100 : // Y(n-2) * Cy(n-2) = YC(n-2)
        iir_state <= #`udly 3'b101 ;
    3'b101 : // Y(n-1) * Cy(n-1) = YC(n-1) 
        iir_state <= #`udly 3'b110 ;
    3'b110 : // XC(n) + XC(n-1) + XC(n-2) + YC(n-2) + YC(n-1) = Y(n)   
    if (iir_done  )
        iir_state <= #`udly 3'b111 ;
    else 
        iir_state <= #`udly 3'b001 ;
    3'b111 :
        iir_state <= #`udly 3'b000 ;
    default :
        iir_state <= #`udly 3'b000 ;             
    endcase
end     

always @(posedge clk or negedge rstn )
if (!rstn )
    tap_cnt  <= #`udly 3'b000 ;
else if(iir_ext_st )
    tap_cnt  <= #`udly 3'b000 ;
else if(iir_add_st & !iir_done )
    tap_cnt  <= #`udly tap_cnt + 1'b1 ;

//////////////////////////////////////////////////////////////////////////

wire        xc1_z0_sel = (tap_cnt == 3'b000) & iir_xc0_st ;
wire        xc1_z1_sel = (tap_cnt == 3'b000) & iir_xc1_st ;
wire        xc1_z2_sel = (tap_cnt == 3'b000) & iir_xc2_st ;
wire        yc1_z2_sel = (tap_cnt == 3'b000) & iir_yc2_st ;
wire        yc1_z1_sel = (tap_cnt == 3'b000) & iir_yc1_st ;
wire        xc2_z0_sel = (tap_cnt == 3'b001) & iir_xc0_st ;
wire        xc2_z1_sel = (tap_cnt == 3'b001) & iir_xc1_st ;
wire        xc2_z2_sel = (tap_cnt == 3'b001) & iir_xc2_st ;
wire        yc2_z2_sel = (tap_cnt == 3'b001) & iir_yc2_st ;
wire        yc2_z1_sel = (tap_cnt == 3'b001) & iir_yc1_st ;
wire        xc3_z0_sel = (tap_cnt == 3'b010) & iir_xc0_st ;
wire        xc3_z1_sel = (tap_cnt == 3'b010) & iir_xc1_st ;
wire        xc3_z2_sel = (tap_cnt == 3'b010) & iir_xc2_st ;
wire        yc3_z2_sel = (tap_cnt == 3'b010) & iir_yc2_st ;
wire        yc3_z1_sel = (tap_cnt == 3'b010) & iir_yc1_st ; 
wire        xc4_z0_sel = (tap_cnt == 3'b011) & iir_xc0_st ;
wire        xc4_z1_sel = (tap_cnt == 3'b011) & iir_xc1_st ;
wire        xc4_z2_sel = (tap_cnt == 3'b011) & iir_xc2_st ;
wire        yc4_z2_sel = (tap_cnt == 3'b011) & iir_yc2_st ;
wire        yc4_z1_sel = (tap_cnt == 3'b011) & iir_yc1_st ; 
wire        xc5_z0_sel = (tap_cnt == 3'b100) & iir_xc0_st ;
wire        xc5_z1_sel = (tap_cnt == 3'b100) & iir_xc1_st ;
wire        xc5_z2_sel = (tap_cnt == 3'b100) & iir_xc2_st ;
wire        yc5_z2_sel = (tap_cnt == 3'b100) & iir_yc2_st ;
wire        yc5_z1_sel = (tap_cnt == 3'b100) & iir_yc1_st ; 
wire        xc6_z0_sel = (tap_cnt == 3'b101) & iir_xc0_st ;
wire        xc6_z1_sel = (tap_cnt == 3'b101) & iir_xc1_st ;
wire        xc6_z2_sel = (tap_cnt == 3'b101) & iir_xc2_st ;
wire        yc6_z2_sel = (tap_cnt == 3'b101) & iir_yc2_st ;
wire        yc6_z1_sel = (tap_cnt == 3'b101) & iir_yc1_st ; 

wire[17:0]  y1_z1 = x2    ;
wire[17:0]  y1_z2 = x2_z1 ;    
wire[17:0]  y2_z1 = x3    ;
wire[17:0]  y2_z2 = x3_z1 ;    
wire[17:0]  y3_z1 = x4    ;
wire[17:0]  y3_z2 = x4_z1 ;    
reg [17:0]  y4_z1 ;
reg [17:0]  y4_z2 ;   
wire[17:0]  y5_z1 = x6    ;
wire[17:0]  y5_z2 = x6_z1 ;    
reg [17:0]  y6_z1 ;
reg [17:0]  y6_z2 ;    

wire[17:0]  a_mul    = {18{xc1_z0_sel}} & x1        |
                       {18{xc1_z1_sel}} & x1_z1     |
                       {18{xc1_z2_sel}} & x1_z2     |
                       {18{yc1_z2_sel}} & y1_z2     |
                       {18{yc1_z1_sel}} & y1_z1     |                       
                       {18{xc2_z0_sel}} & x2        |
                       {18{xc2_z1_sel}} & x2_z1     |
                       {18{xc2_z2_sel}} & x2_z2     |
                       {18{yc2_z2_sel}} & y2_z2     |
                       {18{yc2_z1_sel}} & y2_z1     |
                       {18{xc3_z0_sel}} & x3        |
                       {18{xc3_z1_sel}} & x3_z1     |
                       {18{xc3_z2_sel}} & x3_z2     |
                       {18{yc3_z2_sel}} & y3_z2     |
                       {18{yc3_z1_sel}} & y3_z1     |
                       {18{xc4_z0_sel}} & x4        |
                       {18{xc4_z1_sel}} & x4_z1     |
                       {18{xc4_z2_sel}} & x4_z2     |
                       {18{yc4_z2_sel}} & y4_z2     |
                       {18{yc4_z1_sel}} & y4_z1     |
                       {18{xc5_z0_sel}} & x5        |
                       {18{xc5_z1_sel}} & x5_z1     |
                       {18{xc5_z2_sel}} & x5_z2     |
                       {18{yc5_z2_sel}} & y5_z2     |
                       {18{yc5_z1_sel}} & y5_z1     |
                       {18{xc6_z0_sel}} & x6        |
                       {18{xc6_z1_sel}} & x6_z1     |
                       {18{xc6_z2_sel}} & x6_z2     |
                       {18{yc6_z2_sel}} & y6_z2     |
                       {18{yc6_z1_sel}} & y6_z1     ;
                      
// Coefficent Selection                       
wire[17:0]  b_mul    = {18{xc1_z0_sel}} & 18'h03fb5 |
                       {18{xc1_z1_sel}} & 18'h07177 |
                       {18{xc1_z2_sel}} & 18'h03fb5 |
                       {18{yc1_z2_sel}} & 18'h321cb |
                       {18{yc1_z1_sel}} & 18'h0ed53 |                       
                       {18{xc2_z0_sel}} & 18'h02895 |
                       {18{xc2_z1_sel}} & 18'h00328 |
                       {18{xc2_z2_sel}} & 18'h02895 |
                       {18{yc2_z2_sel}} & 18'h3c684 |
                       {18{yc2_z1_sel}} & 18'h0e528 |
                       {18{xc3_z0_sel}} & 18'h0445e |
                       {18{xc3_z1_sel}} & 18'h0348b |
                       {18{xc3_z2_sel}} & 18'h0445e |
                       {18{yc3_z2_sel}} & 18'h360f6 |
                       {18{yc3_z1_sel}} & 18'h0e1c2 |
                       {18{xc4_z0_sel}} & 18'h047a6 |
                       {18{xc4_z1_sel}} & 18'h3f197 |
                       {18{xc4_z2_sel}} & 18'h047a6 |
                       {18{yc4_z2_sel}} & 18'h39d2c |
                       {18{yc4_z1_sel}} & 18'h0e1f0 |
                       {18{xc5_z0_sel}} & 18'h0FA7B |  // 18'h0F64C |
                       {18{xc5_z1_sel}} & 18'h20B0A |  // 18'h2136A |
                       {18{xc5_z2_sel}} & 18'h0FA7B |  // 18'h0F64C |
                       {18{yc5_z2_sel}} & 18'h30AE9 |  // 18'h312FB |
                       {18{yc5_z1_sel}} & 18'h1F4D9 |  // 18'h1EC45 |
                       {18{xc6_z0_sel}} & 18'h0FA7B |  // 18'h0F64C |
                       {18{xc6_z1_sel}} & 18'h20B0A |  // 18'h2136A |
                       {18{xc6_z2_sel}} & 18'h0FA7B |  // 18'h0F64C |
                       {18{yc6_z2_sel}} & 18'h30AE9 |  // 18'h312FB |
                       {18{yc6_z1_sel}} & 18'h1F4D9 ;  // 18'h1EC45 ;                     

wire[16:0]  a_value  = a_mul[17] ? {~a_mul[16:0] + 1'b1} : a_mul[16:0] ;
wire[16:0]  b_value  = b_mul[17] ? {~b_mul[16:0] + 1'b1} : b_mul[16:0] ;
wire[33:0]  ab_value = a_value * b_value ;                        
wire        ab_sign  = a_mul[17] ^ b_mul[17] ;
                        
wire[35:0]  data_mul = (ab_value == 34'h0_0000_0000) ? 36'h0_0000_0000 :
                       ab_sign ? {2'b11, {~ab_value[33:0] + 1'b1}} : {2'b00, ab_value[33:0]};