dac_test_black_box1_wrapper.v

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//-----------------------------------------------------------------
// System Generator Verilog source file.
// Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
// Reproduction or reuse, in any form, without the explicit written
// consent of Xilinx, Inc., is strictly prohibited.
//-----------------------------------------------------------------

`define false 0
`define true 1

module dac_test_black_box1_wrapper( din,
                                    rstn,
                                    clk,
                                    ce,
                                    dout );
  input   [11:0] din;
  input          rstn;
  input          clk;
  input          ce;
  output  [31:0] dout;
  wire   [11:0] din_wire;
  wire         rstn_wire;
  wire         clk_wire;
  wire         ce_wire;
  wire   [31:0] dout_wire;

  assign  din_wire = din;
  assign rstn_wire = rstn;
  assign  clk_wire = clk;
  assign   ce_wire = ce;
  assign      dout = dout_wire;


  fir_top dac_test_black_box1( .din(din_wire),
                               .rstn(rstn_wire),
                               .clk(clk_wire),
                               .ce(ce_wire),
                               .dout(dout_wire) );


endmodule  // dac_test_black_box1_wrapper