📄 dac_test.err
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num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat1"
Ports [2, 1]
Position [140, 111, 180, 169]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat10"
Ports [2, 1]
Position [270, 336, 310, 394]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat11"
Ports [2, 1]
Position [270, 141, 310, 199]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat12"
Ports [2, 1]
Position [335, 241, 375, 299]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat2"
Ports [2, 1]
Position [205, 81, 245, 139]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat3"
Ports [2, 1]
Position [140, 171, 180, 229]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat4"
Ports [2, 1]
Position [140, 231, 180, 289]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat5"
Ports [2, 1]
Position [205, 201, 245, 259]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat6"
Ports [2, 1]
Position [140, 291, 180, 349]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat7"
Ports [2, 1]
Position [140, 351, 180, 409]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat8"
Ports [2, 1]
Position [205, 321, 245, 379]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat9"
Ports [2, 1]
Position [140, 411, 180, 469]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Outport
Name "dout_rep"
Position [400, 263, 430, 277]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Concat"
SrcPort 1
Points [5, 0]
DstBlock "Concat2"
DstPort 1
}
Line {
SrcBlock "Concat1"
SrcPort 1
Points [5, 0]
DstBlock "Concat2"
DstPort 2
}
Line {
SrcBlock "Concat3"
SrcPort 1
Points [5, 0]
DstBlock "Concat5"
DstPort 1
}
Line {
SrcBlock "Concat4"
SrcPort 1
Points [5, 0]
DstBlock "Concat5"
DstPort 2
}
Line {
SrcBlock "Concat6"
SrcPort 1
Points [5, 0]
DstBlock "Concat8"
DstPort 1
}
Line {
SrcBlock "Concat7"
SrcPort 1
Points [5, 0]
DstBlock "Concat8"
DstPort 2
}
Line {
SrcBlock "Concat9"
SrcPort 1
Points [70, 0]
DstBlock "Concat10"
DstPort 2
}
Line {
SrcBlock "Concat2"
SrcPort 1
Points [5, 0]
DstBlock "Concat11"
DstPort 1
}
Line {
SrcBlock "Concat5"
SrcPort 1
Points [5, 0]
DstBlock "Concat11"
DstPort 2
}
Line {
SrcBlock "Concat8"
SrcPort 1
DstBlock "Concat10"
DstPort 1
}
Line {
SrcBlock "Concat11"
SrcPort 1
Points [5, 0]
DstBlock "Concat12"
DstPort 1
}
Line {
SrcBlock "Concat10"
SrcPort 1
Points [5, 0]
DstBlock "Concat12"
DstPort 2
}
Line {
SrcBlock "din"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
Labels [1, 0]
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
DstBlock "Concat1"
DstPort 2
}
Branch {
Points [0, 30]
Branch {
DstBlock "Concat3"
DstPort 1
}
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
DstBlock "Concat9"
DstPort 1
}
Branch {
Points [0, 30]
DstBlock "Concat9"
DstPort 2
}
}
Branch {
DstBlock "Concat7"
DstPort 2
}
}
Branch {
DstBlock "Concat7"
DstPort 1
}
}
Branch {
DstBlock "Concat6"
DstPort 2
}
}
Branch {
DstBlock "Concat6"
DstPort 1
}
}
Branch {
DstBlock "Concat4"
DstPort 2
}
}
Branch {
DstBlock "Concat4"
DstPort 1
}
}
Branch {
DstBlock "Concat3"
DstPort 2
}
}
}
}
Branch {
DstBlock "Concat1"
DstPort 1
}
}
Branch {
Labels [1, 0]
DstBlock "Concat"
DstPort 2
}
}
Branch {
DstBlock "Concat"
DstPort 1
}
}
Line {
SrcBlock "Concat12"
SrcPort 1
DstBlock "dout_rep"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "Slice"
Ports [1, 1]
Position [95, 247, 140, 273]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Lower Bit Location + Width"
nbits "1"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Slice1"
Ports [1, 1]
Position [95, 282, 140, 308]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Upper Bit Location + Width"
nbits "13"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "r1"
Ports [2, 1]
Position [600, 149, 645, 231]
SourceBlock "xbsIndex_r3/Register"
SourceType "Xilinx Register Block"
init "2^13"
reg_only_valid on
explicit_period on
period "1"
rst off
en on
out_en off
dbl_ovrd off
show_param off
xl_area "[7 14 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Outport
Name "ref_shifter"
Position [685, 183, 715, 197]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Logical"
SrcPort 1
DstBlock "r1"
DstPort 1
}
Line {
SrcBlock "Logical1"
SrcPort 1
DstBlock "Logical"
DstPort 1
}
Line {
SrcBlock "Logical2"
SrcPort 1
Points [15, 0]
DstBlock "Logical1"
DstPort 1
}
Line {
SrcBlock "Logical3"
SrcPort 1
Points [15, 0]
DstBlock "Logical1"
DstPort 2
}
Line {
SrcBlock "Slice"
SrcPort 1
Points [5, 0]
Branch {
Points [0, -155]
DstBlock "Inverter3"
DstPort 1
}
Branch {
DstBlock "Concat"
DstPort 1
}
}
Line {
SrcBlock "Slice1"
SrcPort 1
DstBlock "Concat"
DstPort 2
}
Line {
SrcBlock "mask"
SrcPort 1
Points [15, 0]
Branch {
Points [0, 40]
Branch {
DstBlock "Slice"
DstPort 1
}
Branch {
Points [0, 35]
DstBlock "Slice1"
DstPort 1
}
}
Branch {
DstBlock "Logical3"
DstPort 2
}
}
Line {
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