dac_test_black_box_wrapper.v

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//-----------------------------------------------------------------
// System Generator Verilog source file.
// Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
// Reproduction or reuse, in any form, without the explicit written
// consent of Xilinx, Inc., is strictly prohibited.
//-----------------------------------------------------------------

`define false 0
`define true 1

module dac_test_black_box_wrapper( din,
                                   fltsel,
                                   rstn,
                                   clk,
                                   ce,
                                   clk_1,
                                   ce_1,
                                   dout );
  input   [17:0] din;
  input          fltsel;
  input          rstn;
  input          clk;
  input          ce;
  input          clk_1;
  input          ce_1;
  output  [17:0] dout;
  wire   [17:0] din_wire;
  wire         fltsel_wire;
  wire         rstn_wire;
  wire         clk_wire;
  wire         ce_wire;
  wire         clk_1_wire;
  wire         ce_1_wire;
  wire   [17:0] dout_wire;

  assign    din_wire = din;
  assign fltsel_wire = fltsel;
  assign   rstn_wire = rstn;
  assign    clk_wire = clk;
  assign     ce_wire = ce;
  assign  clk_1_wire = clk_1;
  assign   ce_1_wire = ce_1;
  assign        dout = dout_wire;


  iir_filter dac_test_black_box( .din(din_wire),
                                 .fltsel(fltsel_wire),
                                 .rstn(rstn_wire),
                                 .clk(clk_wire),
                                 .ce(ce_wire),
                                 .clk_1(clk_1_wire),
                                 .ce_1(ce_1_wire),
                                 .dout(dout_wire) );


endmodule  // dac_test_black_box_wrapper