📄 sysgenadcdac.mdl
字号:
}
}
Line {
SrcBlock "Concat12"
SrcPort 1
DstBlock "dout_rep"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "Slice"
Ports [1, 1]
Position [95, 247, 140, 273]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Lower Bit Location + Width"
nbits "1"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Slice1"
Ports [1, 1]
Position [95, 282, 140, 308]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Upper Bit Location + Width"
nbits "13"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "r1"
Ports [2, 1]
Position [600, 149, 645, 231]
SourceBlock "xbsIndex_r3/Register"
SourceType "Xilinx Register Block"
init "2^13"
reg_only_valid on
explicit_period on
period "1"
rst off
en on
out_en off
dbl_ovrd off
show_param off
xl_area "[7 14 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Outport
Name "ref_shifter"
Position [685, 183, 715, 197]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Logical"
SrcPort 1
DstBlock "r1"
DstPort 1
}
Line {
SrcBlock "Logical1"
SrcPort 1
DstBlock "Logical"
DstPort 1
}
Line {
SrcBlock "Logical2"
SrcPort 1
Points [15, 0]
DstBlock "Logical1"
DstPort 1
}
Line {
SrcBlock "Logical3"
SrcPort 1
Points [15, 0]
DstBlock "Logical1"
DstPort 2
}
Line {
SrcBlock "Slice"
SrcPort 1
Points [5, 0]
Branch {
Points [0, -155]
DstBlock "Inverter3"
DstPort 1
}
Branch {
DstBlock "Concat"
DstPort 1
}
}
Line {
SrcBlock "Slice1"
SrcPort 1
DstBlock "Concat"
DstPort 2
}
Line {
SrcBlock "mask"
SrcPort 1
Points [15, 0]
Branch {
Points [0, 40]
Branch {
DstBlock "Slice"
DstPort 1
}
Branch {
Points [0, 35]
DstBlock "Slice1"
DstPort 1
}
}
Branch {
DstBlock "Logical3"
DstPort 2
}
}
Line {
SrcBlock "Concat"
SrcPort 1
Points [260, 0]
DstBlock "Logical"
DstPort 2
}
Line {
SrcBlock "AgtR"
SrcPort 1
DstBlock "Inverter2"
DstPort 1
}
Line {
SrcBlock "Replicator1"
SrcPort 1
DstBlock "Logical2"
DstPort 2
}
Line {
SrcBlock "Replicator2"
SrcPort 1
DstBlock "Logical3"
DstPort 1
}
Line {
SrcBlock "r1"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "ref_shifter"
DstPort 1
}
Branch {
Points [0, 0; 0, -165; -350, 0; 0, 35]
DstBlock "Logical2"
DstPort 1
}
}
Line {
SrcBlock "shift"
SrcPort 1
DstBlock "r1"
DstPort 2
}
Line {
SrcBlock "Inverter3"
SrcPort 1
DstBlock "Replicator1"
DstPort 1
}
Line {
SrcBlock "Inverter2"
SrcPort 1
DstBlock "Replicator2"
DstPort 1
}
Annotation {
Name "The Reference Shifter produces the DAC "
"input and eventually the\nADC output. The shifter starts with the MSB set to"
" 1, so an\ninitial voltage comparison is forced to take place. \n\nThe subsy"
"stem performs sequential comparisons based on the \nshifter output and the co"
"mparator input signal AgtR. If the current\nshifter output produces a voltag"
"e greater than the analog voltage,\nit sets the current bit (indicated by the"
" mask) to 0, and moves on \nthe next bit position."
Position [235, 365]
HorizontalAlignment "left"
DropShadow on
FontName "Arial"
FontSize 11
}
Annotation {
Name "Register 'r1' is initialized with the M"
"SB\nset to 1."
Position [535, 270]
HorizontalAlignment "left"
DropShadow on
FontName "Arial"
FontSize 11
}
}
}
Block {
BlockType Reference
Name "Relational1"
Ports [2, 1]
Position [270, 384, 310, 451]
ShowName off
SourceBlock "xbsIndex_r3/Relational"
SourceType "Xilinx Relational Block"
mode "a=b"
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[1 0 0 2 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Slice"
Ports [1, 1]
Position [265, 282, 315, 308]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Lower Bit Location + Width"
nbits "1"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output on
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "dec_fstm_cnt"
Ports [1, 1]
Position [380, 544, 420, 566]
ShowName off
SourceBlock "xbsIndex_r3/Delay"
SourceType "Xilinx Delay Block"
latency "1"
reg_retiming off
explicit_period off
period "1"
en off
accept_only_valid off
init_zero on
dbl_ovrd off
show_param off
xl_area "[1 1 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "l1"
Ports [3, 1]
Position [380, 281, 425, 349]
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "AND"
inputs "3"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
align_bp on
latency "1"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[1 1 0 1 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "l2"
Ports [2, 1]
Position [380, 404, 425, 471]
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "AND"
inputs "2"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
align_bp on
latency "1"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[1 1 0 1 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "rel1"
Ports [2, 1]
Position [270, 519, 310, 586]
SourceBlock "xbsIndex_r3/Relational"
SourceType "Xilinx Relational Block"
mode "a=b"
latency "1"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[4 1 0 7 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "sample2"
Ports [1, 1]
Position [380, 369, 420, 391]
ShowName off
SourceBlock "xbsIndex_r3/Delay"
SourceType "Xilinx Delay Block"
latency "1"
reg_retiming off
explicit_period on
period "1"
en off
accept_only_valid off
init_zero on
dbl_ovrd off
show_param off
xl_area "[1 1 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Outport
Name "DAC_driver"
Position [460, 108, 490, 122]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "ADCout"
Position [460, 183, 490, 197]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "ADC_Sampled"
Position [460, 308, 490, 322]
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "sample"
Position [460, 373, 490, 387]
Port "4"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "rel1"
DstPort 2
}
Line {
SrcBlock "DAC Sample\nCounter"
SrcPort 1
DstBlock "rel1"
DstPort 1
}
Line {
SrcBlock "sample2"
SrcPort 1
DstBlock "sample"
DstPort 1
}
Line {
SrcBlock "l1"
SrcPort 1
Points [0, 0; 5, 0]
Branch {
DstBlock "ADC_Sampled"
DstPort 1
}
Branch {
Points [0, -45; -85, 0; 0, -60]
DstBlock "ADCOut \nRegister"
DstPort 2
}
}
Line {
SrcBlock "Constant1"
SrcPort 1
DstBlock "Relational1"
DstPort 2
}
Line {
SrcBlock "'c1'"
SrcPort 1
DstBlock "FSTM\nCounter"
DstPort 2
}
Line {
SrcBlock "FSTM\nCounter"
SrcPort 1
DstBlock "Relational1"
DstPort 1
}
Line {
SrcBlock "dec_fstm_cnt"
SrcPort 1
Points [10, 0; 0, -60; -335, 0; 0, -60]
DstBlock "FSTM\nCounter"
DstPort 3
}
Line {
SrcBlock "Mask\nShifter"
SrcPort 1
Points [10, 0; 0, 35]
Branch {
Points [0, 145]
DstBlock "Slice"
DstPort 1
}
Branch {
DstBlock "Reference\nShifter\n"
DstPort 3
}
}
Line {
SrcBlock "Reference\nShifter\n"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
DstBlock "DAC_driver"
DstPort 1
}
Branch {
Points [0, 50]
DstBlock "ADCOut \nRegister"
DstPort 1
}
}
Line {
SrcBlock "AgtR"
SrcPort 1
Points [175, 0]
DstBlock "Reference\nShifter\n"
DstPort 1
}
Line {
SrcBlock "Slice"
SrcPort 1
Points [5, 0; 20, 0]
Branch {
DstBlock "l1"
DstPort 1
}
Branch {
Points [0, 85]
DstBlock "sample2"
DstPort 1
}
}
Line {
SrcBlock ⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -