📄 sysgenadcdac.mdl
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}
Branch {
Points [0, 35]
DstBlock "Slicer"
DstPort 1
}
}
}
Annotation {
Name "The Mask Shifter controls the bit sampl"
"e sequence. The width\nof the mask must be the same width as the mask input."
" When \nthe 'shift' signal is asserted, the subsystem shifts the mask 1\nbit"
" to the right. The result is a 'one hot' repeating sequence. \nThe Reference"
" Shifter uses this sequence, or mask, as a basis\non which comparisons are ma"
"de and bits are set in the \nconstructed ADC sample. "
Position [32, 264]
HorizontalAlignment "left"
DropShadow on
FontName "Arial"
FontSize 11
}
Annotation {
Name "Register block 'mask_reg' is initialize"
"d\nwith the unshifted mask."
Position [267, 174]
HorizontalAlignment "left"
DropShadow on
FontName "Arial"
FontSize 11
}
Annotation {
Position [500, 212]
}
}
}
Block {
BlockType SubSystem
Name "Reference\nShifter\n"
Ports [3, 1]
Position [255, 64, 330, 166]
BackgroundColor "lightBlue"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Reference\nShifter\n"
Location [264, 74, 1014, 724]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 262
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "AgtR"
Position [25, 168, 55, 182]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "shift"
Position [550, 203, 580, 217]
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "mask"
Position [25, 213, 55, 227]
Port "3"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "Concat"
Ports [2, 1]
Position [170, 240, 210, 315]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Inverter2"
Ports [1, 1]
Position [170, 164, 210, 186]
ShowName off
SourceBlock "xbsIndex_r3/Inverter"
SourceType "Xilinx Inverter"
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[0 0 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Inverter3"
Ports [1, 1]
Position [170, 94, 210, 116]
ShowName off
SourceBlock "xbsIndex_r3/Inverter"
SourceType "Xilinx Inverter"
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[0 0 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Logical"
Ports [2, 1]
Position [490, 122, 540, 213]
ShowName off
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "OR"
inputs "2"
precision "User Defined"
arith_type "Unsigned"
n_bits "14"
bin_pt "0"
align_bp on
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[14 0 0 14 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Logical1"
Ports [2, 1]
Position [415, 96, 465, 189]
ShowName off
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "AND"
inputs "2"
precision "User Defined"
arith_type "Unsigned"
n_bits "14"
bin_pt "0"
align_bp on
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[14 0 0 14 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Logical2"
Ports [2, 1]
Position [330, 39, 380, 126]
ShowName off
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "AND"
inputs "2"
precision "User Defined"
arith_type "Unsigned"
n_bits "14"
bin_pt "0"
align_bp on
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[14 0 0 14 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Logical3"
Ports [2, 1]
Position [330, 154, 380, 241]
ShowName off
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "NAND"
inputs "2"
precision "User Defined"
arith_type "Unsigned"
n_bits "14"
bin_pt "0"
align_bp on
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[14 0 0 14 0 0 0]"
xl_use_area off
}
Block {
BlockType SubSystem
Name "Replicator1"
Ports [1, 1]
Position [230, 79, 305, 131]
BackgroundColor "lightBlue"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Replicator1"
Location [6, 74, 1026, 752]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "din"
Position [55, 57, 85, 73]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "Concat"
Ports [2, 1]
Position [140, 51, 180, 109]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat1"
Ports [2, 1]
Position [140, 111, 180, 169]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat10"
Ports [2, 1]
Position [270, 336, 310, 394]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat11"
Ports [2, 1]
Position [335, 241, 375, 299]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat12"
Ports [2, 1]
Position [270, 141, 310, 199]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat2"
Ports [2, 1]
Position [205, 81, 245, 139]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat3"
Ports [2, 1]
Position [140, 171, 180, 229]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat4"
Ports [2, 1]
Position [140, 231, 180, 289]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat5"
Ports [2, 1]
Position [205, 201, 245, 259]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat6"
Ports [2, 1]
Position [140, 291, 180, 349]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat7"
Ports [2, 1]
Position [140, 351, 180, 409]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat8"
Ports [2, 1]
Position [205, 321, 245, 379]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat9"
Ports [2, 1]
Position [140, 411, 180, 469]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Outport
Name "dout_rep"
Position [400, 263, 430, 277]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Concat"
SrcPort 1
Points [5, 0]
DstBlock "Concat2"
DstPort 1
}
Line {
SrcBlock "Concat1"
SrcPort 1
Points [5, 0]
DstBlock "Concat2"
DstPort 2
}
Line {
SrcBlock "Concat3"
SrcPort 1
Points [5, 0]
DstBlock "Concat5"
DstPort 1
}
Line {
SrcBlock "Concat4"
SrcPort 1
Points [5, 0]
DstBlock "Concat5"
DstPort 2
}
Line {
SrcBlock "Concat6"
SrcPort 1
Points [5, 0]
DstBlock "Concat8"
DstPort 1
}
Line {
SrcBlock "Concat7"
SrcPort 1
Points [5, 0]
DstBlock "Concat8"
DstPort 2
}
Line {
SrcBlock "Concat9"
SrcPort 1
Points [70, 0]
DstBlock "Concat10"
DstPort 2
}
Line {
SrcBlock "Concat2"
SrcPort 1
Points [5, 0]
DstBlock "Concat12"
DstPort 1
}
Line {
SrcBlock "Concat5"
SrcPort 1
Points [5, 0]
DstBlock "Concat12"
DstPort 2
}
Line {
SrcBlock "Concat8"
SrcPort 1
DstBlock "Concat10"
DstPort 1
}
Line {
SrcBlock "Concat12"
SrcPort 1
Points [5, 0]
DstBlock "Concat11"
DstPort 1
}
Line {
SrcBlock "Concat10"
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