📄 sysgenadcdac.mdl
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LogicDataType "uint(8)"
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SampleTime "-1"
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AttributesFormatString "System\\nGenerator"
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UserData "DataTag0"
SourceBlock "xbsIndex_r3/ System Generator"
SourceType "Xilinx System Generator"
ShowPortLabels on
xilinxfamily "Spartan2"
part "xc2s15"
speed "-6"
package "cs144"
synthesis_tool "XST"
directory "./sysgenADCDACysgen"
testbench on
simulink_period "1"
sysclk_period "6.8"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
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"ts reserved.\n\nThis file contains proprietary, confidential information of X"
"ilinx, Inc., is distributed under license\nfrom Xilinx, Inc., and may be used"
", copied and/or disclosed only pursuant to the terms of a valid license\nagre"
"ement with Xilinx, Inc. Xilinx hereby grants you a license to use this file s"
"olely for design,\nsimulation, implementation and creation of design files li"
"mited to Xilinx devices or technologies. Use \nwith non-Xilinx devices or tec"
"hnologies is expressly prohibited and immediately terminates your license \nu"
"nless covered by a separate agreement.\n\nXilinx is providing this design, co"
"de, or information \"as-is\" solely for use in developing programs and \nsolu"
"tions for Xilinx devices, with no obligation on the part of Xilinx to provide"
" support. By providing\nthis design, code, or information as one possible imp"
"lementation of this feature, application or standard,\nXilinx is making no re"
"presentation that this implementation is free from any claims of infringement"
". You\nare responsible for obtaining any rights you may require for your impl"
"ementation. Xilinx expressly disclaims\nany warranty whatsoever with respect "
"to the adequacy of the implementation, including but not limited to any\nwarr"
"anties or representations that this implementation is free from claims of inf"
"ringement, implied warranties\nof merchantability or fitness for a particular"
" purpose.\n\nXilinx products are not intended for use in life support applian"
"ces, devices, or systems. Use in such \napplications is expressly prohibited."
"\n\nAny modifications that are made to the Source Code are done at the user's"
" sole risk and will be unsupported. \n\nThis copyright and support notice mus"
"t be retained as part of this text at all times. \n(c) Copyright 1995-2004 Xi"
"linx, Inc. All rights reserved."
Position [6, 192]
HorizontalAlignment "left"
FontName "Arial"
FontSize 12
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Block {
BlockType SubSystem
Name "ADC\n(XAPP155)"
Ports [1, 4]
Position [225, 99, 325, 206]
BackgroundColor "lightBlue"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "ADC\n(XAPP155)"
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Position [30, 28, 60, 42]
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Port "1"
IconDisplay "Port number and signal name"
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BlockType Reference
Name "'c1'"
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SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "Fstm"
equ "P=C"
arith_type "Unsigned"
n_bits "4"
bin_pt "0"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
iostate "0"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "ADCOut \nRegister"
Ports [2, 1]
Position [370, 141, 430, 234]
SourceBlock "xbsIndex_r3/Register"
SourceType "Xilinx Register Block"
init "0"
reg_only_valid off
explicit_period off
period "1"
rst off
en on
out_en off
dbl_ovrd off
show_param off
xl_area "[7 14 0 0 0 0 0]"
xl_use_area off
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BlockType Reference
Name "Constant"
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Position [210, 561, 250, 579]
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SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "0"
equ "P=C"
arith_type "Unsigned"
n_bits "14"
bin_pt "0"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
iostate "0"
explicit_period off
period "1"
dbl_ovrd off
}
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BlockType Reference
Name "Constant1"
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Position [210, 426, 250, 444]
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SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "0"
equ "P=C"
arith_type "Unsigned"
n_bits "1"
bin_pt "0"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
iostate "0"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "DAC Sample\nCounter"
Ports [0, 1]
Position [140, 507, 195, 563]
SourceBlock "xbsIndex_r3/Counter"
SourceType "Xilinx Counter Block"
cnt_type "Count Limited"
n_bits "8"
bin_pt "0"
arith_type "Unsigned"
start_count "0"
cnt_to "Inf"
cnt_by_val "1"
operation "Up"
explicit_period off
period "1"
load_pin off
rst off
en off
dbl_ovrd off
show_param off
use_rpm off
gen_core on
xl_area "[7 10 0 13 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "FSTM\nCounter"
Ports [3, 1]
Position [135, 346, 200, 454]
SourceBlock "xbsIndex_r3/Counter"
SourceType "Xilinx Counter Block"
cnt_type "Free Running"
n_bits "4"
bin_pt "0"
arith_type "Unsigned"
start_count "2"
cnt_to "Inf"
cnt_by_val "1"
operation "Down"
explicit_period on
period "1"
load_pin on
rst off
en on
dbl_ovrd off
show_param off
use_rpm off
gen_core on
xl_area "[4 4 0 5 0 0 0]"
xl_use_area off
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DialogController "Simulink.DDGSource"
GotoTag "shift"
TagVisibility "local"
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Block {
BlockType SubSystem
Name "Mask\nShifter"
Ports [1, 1]
Position [125, 65, 195, 165]
BackgroundColor "lightBlue"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Mask\nShifter"
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ModelBrowserVisibility on
ModelBrowserWidth 212
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "shift"
Position [145, 138, 175, 152]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "Concat"
Ports [2, 1]
Position [140, 64, 185, 131]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "LSB Slice"
Ports [1, 1]
Position [75, 70, 120, 90]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Lower Bit Location + Width"
nbits "1"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Slicer"
Ports [1, 1]
Position [75, 105, 120, 125]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Upper Bit Location + Width"
nbits "13"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "mask_reg"
Ports [2, 1]
Position [205, 77, 250, 168]
SourceBlock "xbsIndex_r3/Register"
SourceType "Xilinx Register Block"
init "2^13"
reg_only_valid off
explicit_period on
period "1"
rst off
en on
out_en off
dbl_ovrd off
show_param off
xl_area "[7 14 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Outport
Name "mask"
Position [280, 118, 310, 132]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Concat"
SrcPort 1
DstBlock "mask_reg"
DstPort 1
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Line {
SrcBlock "Slicer"
SrcPort 1
DstBlock "Concat"
DstPort 2
}
Line {
SrcBlock "LSB Slice"
SrcPort 1
DstBlock "Concat"
DstPort 1
}
Line {
SrcBlock "shift"
SrcPort 1
DstBlock "mask_reg"
DstPort 2
}
Line {
SrcBlock "mask_reg"
SrcPort 1
Points [0, 0; 5, 0]
Branch {
DstBlock "mask"
DstPort 1
}
Branch {
Points [0, -75; -215, 0; 0, 30]
Branch {
DstBlock "LSB Slice"
DstPort 1
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