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dbl_ovrd off
}
Block {
BlockType Reference
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Position [140, 171, 180, 229]
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SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
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dbl_ovrd off
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Block {
BlockType Reference
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SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
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Block {
BlockType Reference
Name "Concat5"
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Position [205, 201, 245, 259]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
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Block {
BlockType Reference
Name "Concat6"
Ports [2, 1]
Position [140, 291, 180, 349]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
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Block {
BlockType Reference
Name "Concat7"
Ports [2, 1]
Position [140, 351, 180, 409]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
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Block {
BlockType Reference
Name "Concat8"
Ports [2, 1]
Position [205, 321, 245, 379]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
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Block {
BlockType Reference
Name "Concat9"
Ports [2, 1]
Position [140, 411, 180, 469]
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SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
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Block {
BlockType Outport
Name "dout_rep"
Position [400, 263, 430, 277]
IconDisplay "Port number"
BusOutputAsStruct off
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Line {
SrcBlock "Concat"
SrcPort 1
Points [5, 0]
DstBlock "Concat2"
DstPort 1
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Line {
SrcBlock "Concat1"
SrcPort 1
Points [5, 0]
DstBlock "Concat2"
DstPort 2
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Line {
SrcBlock "Concat3"
SrcPort 1
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DstBlock "Concat5"
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SrcBlock "Concat4"
SrcPort 1
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Line {
SrcBlock "Concat6"
SrcPort 1
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DstBlock "Concat8"
DstPort 1
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Line {
SrcBlock "Concat7"
SrcPort 1
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DstPort 2
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Line {
SrcBlock "Concat9"
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DstBlock "Concat10"
DstPort 2
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Line {
SrcBlock "Concat2"
SrcPort 1
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DstBlock "Concat11"
DstPort 1
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Line {
SrcBlock "Concat5"
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Line {
SrcBlock "Concat8"
SrcPort 1
DstBlock "Concat10"
DstPort 1
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Line {
SrcBlock "Concat11"
SrcPort 1
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DstBlock "Concat12"
DstPort 1
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Line {
SrcBlock "Concat10"
SrcPort 1
Points [5, 0]
DstBlock "Concat12"
DstPort 2
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Line {
SrcBlock "din"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
Labels [1, 0]
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Branch {
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Branch {
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Branch {
DstBlock "Concat1"
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Branch {
DstBlock "Concat3"
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Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
Branch {
Points [0, 30]
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Points [0, 30]
Branch {
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Branch {
DstBlock "Concat9"
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Branch {
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DstBlock "Concat9"
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Branch {
DstBlock "Concat7"
DstPort 2
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Branch {
DstBlock "Concat7"
DstPort 1
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Branch {
DstBlock "Concat6"
DstPort 2
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Branch {
DstBlock "Concat6"
DstPort 1
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Branch {
DstBlock "Concat4"
DstPort 2
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Branch {
DstBlock "Concat4"
DstPort 1
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Branch {
DstBlock "Concat3"
DstPort 2
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Branch {
DstBlock "Concat1"
DstPort 1
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Branch {
Labels [1, 0]
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Branch {
DstBlock "Concat"
DstPort 1
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Line {
SrcBlock "Concat12"
SrcPort 1
DstBlock "dout_rep"
DstPort 1
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Block {
BlockType Reference
Name "Slice"
Ports [1, 1]
Position [95, 247, 140, 273]
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SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Lower Bit Location + Width"
nbits "1"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
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Block {
BlockType Reference
Name "Slice1"
Ports [1, 1]
Position [95, 282, 140, 308]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Upper Bit Location + Width"
nbits "13"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "r1"
Ports [2, 1]
Position [600, 149, 645, 231]
SourceBlock "xbsIndex_r3/Register"
SourceType "Xilinx Register Block"
init "2^13"
reg_only_valid on
explicit_period on
period "1"
rst off
en on
out_en off
dbl_ovrd off
show_param off
xl_area "[7 14 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Outport
Name "ref_shifter"
Position [685, 183, 715, 197]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Logical"
SrcPort 1
DstBlock "r1"
DstPort 1
}
Line {
SrcBlock "Logical1"
SrcPort 1
DstBlock "Logical"
DstPort 1
}
Line {
SrcBlock "Logical2"
SrcPort 1
Points [15, 0]
DstBlock "Logical1"
DstPort 1
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Line {
SrcBlock "Logical3"
SrcPort 1
Points [15, 0]
DstBlock "Logical1"
DstPort 2
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Line {
SrcBlock "Slice"
SrcPort 1
Points [5, 0]
Branch {
Points [0, -155]
DstBlock "Inverter3"
DstPort 1
}
Branch {
DstBlock "Concat"
DstPort 1
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Line {
SrcBlock "Slice1"
SrcPort 1
DstBlock "Concat"
DstPort 2
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Line {
SrcBlock "mask"
SrcPort 1
Points [15, 0]
Branch {
Points [0, 40]
Branch {
DstBlock "Slice"
DstPort 1
}
Branch {
Points [0, 35]
DstBlock "Slice1"
DstPort 1
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Branch {
DstBlock "Logical3"
DstPort 2
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Line {
SrcBlock "Concat"
SrcPort 1
Points [260, 0]
DstBlock "Logical"
DstPort 2
}
Line {
SrcBlock "AgtR"
SrcPort 1
DstBlock "Inverter2"
DstPort 1
}
Line {
SrcBlock "Replicator1"
SrcPort 1
DstBlock "Logical2"
DstPort 2
}
Line {
SrcBlock "Replicator2"
SrcPort 1
DstBlock "Logical3"
DstPort 1
}
Line {
SrcBlock "r1"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "ref_shifter"
DstPort 1
}
Branch {
Points [0, 0; 0, -165; -350, 0; 0, 35]
DstBlock "Logical2"
DstPort 1
}
}
Line {
SrcBlock "shift"
SrcPort 1
DstBlock "r1"
DstPort 2
}
Line {
SrcBlock "Inverter3"
SrcPort 1
DstBlock "Replicator1"
DstPort 1
}
Line {
SrcBlock "Inverter2"
SrcPort 1
DstBlock "Replicator2"
DstPort 1
}
Annotation {
Name "The Reference Shifter produces the DAC "
"input and eventually the\nADC output. The shifter starts with the MSB set to"
" 1, so an\ninitial voltage comparison is forced to take place. \n\nThe subsy"
"stem performs sequential comparisons based on the \nshifter output and the co"
"mparator input signal AgtR. If the current\nshifter output produces a voltag"
"e greater than the analog voltage,\nit sets the current bit (indicated by the"
" mask) to 0, and moves on \nthe next bit position."
Position [235, 365]
HorizontalAlignment "left"
DropShadow on
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