📄 adctest.mdl
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xl_use_area off
}
Block {
BlockType Reference
Name "DAC Sample\nCounter"
Ports [0, 1]
Position [140, 507, 195, 563]
SourceBlock "xbsIndex_r3/Counter"
SourceType "Xilinx Counter Block"
cnt_type "Count Limited"
n_bits "10"
bin_pt "0"
arith_type "Unsigned"
start_count "0"
cnt_to "Inf"
cnt_by_val "1"
operation "Up"
explicit_period off
period "1"
load_pin off
rst off
en off
dbl_ovrd off
show_param off
use_rpm off
gen_core on
xl_area "[7 10 0 13 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "FSTM\nCounter"
Ports [3, 1]
Position [135, 346, 200, 454]
SourceBlock "xbsIndex_r3/Counter"
SourceType "Xilinx Counter Block"
cnt_type "Free Running"
n_bits "4"
bin_pt "0"
arith_type "Unsigned"
start_count "2"
cnt_to "Inf"
cnt_by_val "1"
operation "Down"
explicit_period on
period "1"
load_pin on
rst off
en on
dbl_ovrd off
show_param off
use_rpm off
gen_core on
xl_area "[4 4 0 5 0 0 0]"
xl_use_area off
}
Block {
BlockType From
Name "From7"
Position [30, 357, 75, 373]
ShowName off
DialogController "Simulink.DDGSource"
CloseFcn "tagdialog Close"
GotoTag "shift"
}
Block {
BlockType Goto
Name "Goto2"
Position [455, 432, 495, 448]
ShowName off
DialogController "Simulink.DDGSource"
GotoTag "shift"
TagVisibility "local"
}
Block {
BlockType SubSystem
Name "Mask\nShifter"
Ports [1, 1]
Position [125, 65, 195, 165]
BackgroundColor "lightBlue"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Mask\nShifter"
Location [305, 132, 1105, 802]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "shift"
Position [145, 138, 175, 152]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "Concat"
Ports [2, 1]
Position [140, 64, 185, 131]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "LSB Slice"
Ports [1, 1]
Position [75, 70, 120, 90]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Lower Bit Location + Width"
nbits "1"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Slicer"
Ports [1, 1]
Position [75, 105, 120, 125]
ShowName off
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Upper Bit Location + Width"
nbits "13"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "mask_reg"
Ports [2, 1]
Position [205, 77, 250, 168]
SourceBlock "xbsIndex_r3/Register"
SourceType "Xilinx Register Block"
init "2^13"
reg_only_valid off
explicit_period on
period "1"
rst off
en on
out_en off
dbl_ovrd off
show_param off
xl_area "[7 14 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Outport
Name "mask"
Position [280, 118, 310, 132]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Concat"
SrcPort 1
DstBlock "mask_reg"
DstPort 1
}
Line {
SrcBlock "Slicer"
SrcPort 1
DstBlock "Concat"
DstPort 2
}
Line {
SrcBlock "LSB Slice"
SrcPort 1
DstBlock "Concat"
DstPort 1
}
Line {
SrcBlock "shift"
SrcPort 1
DstBlock "mask_reg"
DstPort 2
}
Line {
SrcBlock "mask_reg"
SrcPort 1
Points [0, 0; 5, 0]
Branch {
DstBlock "mask"
DstPort 1
}
Branch {
Points [0, -75; -215, 0; 0, 30]
Branch {
DstBlock "LSB Slice"
DstPort 1
}
Branch {
Points [0, 35]
DstBlock "Slicer"
DstPort 1
}
}
}
Annotation {
Name "The Mask Shifter controls the bit sampl"
"e sequence. The width\nof the mask must be the same width as the mask input."
" When \nthe 'shift' signal is asserted, the subsystem shifts the mask 1\nbit"
" to the right. The result is a 'one hot' repeating sequence. \nThe Reference"
" Shifter uses this sequence, or mask, as a basis\non which comparisons are ma"
"de and bits are set in the \nconstructed ADC sample. "
Position [32, 264]
HorizontalAlignment "left"
DropShadow on
FontName "Arial"
FontSize 11
}
Annotation {
Name "Register block 'mask_reg' is initialize"
"d\nwith the unshifted mask."
Position [267, 174]
HorizontalAlignment "left"
DropShadow on
FontName "Arial"
FontSize 11
}
Annotation {
Position [500, 212]
}
}
}
Block {
BlockType Scope
Name "RC Network\nOutput\n"
Ports [5]
Position [700, 22, 760, 198]
Location [5, 49, 1029, 743]
Open off
NumInputPorts "5"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "RC Network Output"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
axes4 "%<SignalLabel>"
axes5 "%<SignalLabel>"
}
YMin "-0.1~-5~-5~-5~-5"
YMax "1~5~5~5~5"
DataFormat "StructureWithTime"
MaxDataPoints "5000000"
}
Block {
BlockType Scope
Name "RC Network\nOutput\n1"
Ports [2]
Position [555, 377, 615, 553]
Location [5, 49, 1029, 743]
Open off
NumInputPorts "2"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "RC Network Output"
axes2 "%<SignalLabel>"
}
YMin "-0.1~-5"
YMax "1~5"
SaveName "ScopeData5"
DataFormat "StructureWithTime"
MaxDataPoints "5000000"
}
Block {
BlockType SubSystem
Name "Reference\nShifter\n"
Ports [3, 1]
Position [255, 64, 330, 166]
BackgroundColor "lightBlue"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Reference\nShifter\n"
Location [264, 70, 1022, 720]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "AgtR"
Position [25, 168, 55, 182]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "shift"
Position [550, 203, 580, 217]
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "mask"
Position [25, 213, 55, 227]
Port "3"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "Concat"
Ports [2, 1]
Position [170, 240, 210, 315]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Inverter2"
Ports [1, 1]
Position [170, 164, 210, 186]
ShowName off
SourceBlock "xbsIndex_r3/Inverter"
SourceType "Xilinx Inverter"
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[0 0 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Inverter3"
Ports [1, 1]
Position [170, 94, 210, 116]
ShowName off
SourceBlock "xbsIndex_r3/Inverter"
SourceType "Xilinx Inverter"
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[0 0 0 0 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Logical"
Ports [2, 1]
Position [490, 122, 540, 213]
ShowName off
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "OR"
inputs "2"
precision "User Defined"
arith_type "Unsigned"
n_bits "14"
bin_pt "0"
align_bp on
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[14 0 0 14 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Logical1"
Ports [2, 1]
Position [415, 96, 465, 189]
ShowName off
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "AND"
inputs "2"
precision "User Defined"
arith_type "Unsigned"
n_bits "14"
bin_pt "0"
align_bp on
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[14 0 0 14 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Logical2"
Ports [2, 1]
Position [330, 39, 380, 126]
ShowName off
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "AND"
inputs "2"
precision "User Defined"
arith_type "Unsigned"
n_bits "14"
bin_pt "0"
align_bp on
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[14 0 0 14 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Logical3"
Ports [2, 1]
Position [330, 154, 380, 241]
ShowName off
SourceBlock "xbsIndex_r3/Logical"
SourceType "Xilinx Logical Block"
logical_function "NAND"
inputs "2"
precision "User Defined"
arith_type "Unsigned"
n_bits "14"
bin_pt "0"
align_bp on
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
xl_area "[14 0 0 14 0 0 0]"
xl_use_area off
}
Block {
BlockType SubSystem
Name "Replicator1"
Ports [1, 1]
Position [230, 79, 305, 131]
BackgroundColor "lightBlue"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Replicator1"
Location [6, 74, 1026, 752]
Open off
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