xlcosim_dac_test_modelsim_clk_drvr.vhd

来自「使用ＭＡＴＬＡＢ工具」· VHDL 代码 · 共 40 行

library IEEE;
use IEEE.std_logic_1164.all;

entity xlcosim_dac_test_modelsim_clk_drvr is
    port (
      clk : out std_logic := '0';
      ce_1 : out std_logic := '1';
      ce_2 : out std_logic := '0');
end xlcosim_dac_test_modelsim_clk_drvr;

architecture behavior of xlcosim_dac_test_modelsim_clk_drvr is
  constant half_sys_period : time := 16.666666667 ms;
  signal proto_clk : std_logic := '1';
  signal proto_ce_1 : std_logic := '1';
  signal proto_ce_2 : std_logic := '1';
begin

    Process_proto_clk :  process (proto_clk)
    begin
      if (proto_clk='0') then
        proto_clk <= '1' after (1 * half_sys_period);
      else
        proto_clk <= '0' after (1 * half_sys_period);
      end if;
    end process Process_proto_clk;

    Process_proto_ce_2 :  process (proto_ce_2)
    begin
      if (proto_ce_2='0') then
        proto_ce_2 <= '1' after (2 * half_sys_period);
      else
        proto_ce_2 <= '0' after (2 * half_sys_period);
      end if;
    end process Process_proto_ce_2;

    clk <= transport proto_clk after (1.99*half_sys_period);
    ce_2 <= transport proto_ce_2 after (2*half_sys_period);

end behavior;