📄 fm_test.mdl
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BlockType Product
Name "Divide2"
Ports [2, 1]
Position [500, 357, 530, 388]
Inputs "**"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
RndMeth "Floor"
SaturateOnIntegerOverflow off
SampleTime "Ts"
}
Block {
BlockType Reference
Name "ModelSim"
Ports []
Position [188, 742, 256, 798]
FontName "Arial"
SourceBlock "xbsIndex_r3/ModelSim"
SourceType "ModelSim HDL Co-Simulation Interface"
dir "./modelsim"
waveform "off"
leave_open "off"
skip_compile "off"
custom_scripts "off"
startup_timeout "40"
}
Block {
BlockType SubSystem
Name "More Info"
Ports []
Position [770, 766, 895, 844]
DropShadow on
ShowName off
FontName "Arial"
FontSize 12
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskDisplay "disp('Double click\\n for\\n more information.'"
")"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "More Info"
Location [202, 74, 1022, 724]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Annotation {
Name "Demonstration of A/D and Delta-Sigma D/A Co"
"nversion"
Position [298, 22]
FontName "Arial"
FontSize 14
FontWeight "bold"
}
Annotation {
Name "This model implements a 14-bit analog to di"
"gital converter (ADC) and a digital to analog converter \n(DAC) for Virtex an"
"d Virtex derivative devices. The model is based on the delta-sigma DAC and A"
"DC\nimplementations described, respectively, in Xilinx App. Notes 154 and 155"
" by John Logue. Both\ndocuments can be found at \n\n http://www.xilinx.com/"
"apps/appsweb.htm\n\nThe ADC requires feedback from the DAC to compute output "
"samples. The DAC output is a pulse \nstring whose duty cycle is proportional"
" to the amplitude of the desired output voltage. XAPP154 \ndescribes a low-p"
"ass filter on the DAC output implemented with an RC network. Here the RC net"
"work\nis simulated using a transfer function block. XAPP155 specifies an op-"
"amp circuit on the input of\nthe ADC. In this model, the op-amp is replaced "
"by a relational block.\n\nWhen simulating this model, the behavior is best vi"
"ewed with the simulation duration set to Inf. The \nDAC input display shows "
"the a binary representation of the DAC input and illustrates the binary searc"
"h\nused by the ADC to constructs a digital sample of the input voltage (in th"
"is case .73). \n\nThis design occupies 51 slices (26 %) of an xc2s15-6 part "
"and runs at 150 MHz \n(advanced speeds files 1.96, ISE 4.2i software)."
Position [20, 40]
HorizontalAlignment "left"
VerticalAlignment "top"
FontName "Arial"
FontSize 12
}
}
}
Block {
BlockType Reference
Name "PN Spectrum1"
Ports [1]
Position [675, 349, 715, 401]
SourceBlock "dspsnks4/Spectrum\nScope"
SourceType "Spectrum Scope"
ShowPortLabels off
ScopeProperties on
Domain "Frequency"
HorizSpan "1"
UseBuffer on
BufferSize "1024"
Overlap "32"
inpFftLenInherit on
FFTlength "1024"
numAvg "128"
DisplayProperties off
AxisGrid on
Memory off
FrameNumber on
AxisLegend off
AxisZoom off
OpenScopeAtSimStart on
OpenScopeImmediately off
FigPos "[232 246 560 420]"
AxisProperties off
XUnits "Hertz"
XRange "[0...Fs/2]"
InheritXIncr on
XIncr "1.0"
XLabel "Samples"
YUnits "dB"
YMin "-29.8376647752428"
YMax "81.4857475937277"
YLabel "Magnitude-squared, dB"
LineProperties off
LineStyles "-"
LineMarkers "None"
LineColors "[0 0 1]"
wintypeSpecScope "Hann"
RsSpecScope "50"
betaSpecScope "5"
winsampSpecScope "Periodic"
}
Block {
BlockType Reference
Name "Ramp"
Ports [0, 1]
Position [75, 240, 105, 270]
SourceBlock "simulink/Sources/Ramp"
SourceType "Ramp"
ShowPortLabels on
slope "2*pi/(25*Ts)"
start "0"
X0 "0"
VectorParams1D on
}
Block {
BlockType Reference
Name "Resource Estimator"
Tag "resEstTag"
Ports []
Position [655, 780, 708, 833]
ShowName off
AttributesFormatString "Resource\\nEstimator"
FontName "Arial"
SourceBlock "xbsIndex_r3/Resource Estimator"
SourceType "Xilinx Resource Estimator Block"
ShowPortLabels "on"
xl_estimator_area "[122 78 0 117 2 0 0]"
xl_use_estimator_area "off"
simulink_period "1"
mrp_directory "./sysgenADCDACysgen"
}
Block {
BlockType SignalGenerator
Name "Signal\nGenerator"
Ports [0, 1]
Position [80, 355, 110, 385]
Amplitude "500/(2*pi)"
Frequency "1/(10000*Ts)"
}
Block {
BlockType SignalGenerator
Name "Signal\nGenerator1"
Ports [0, 1]
Position [510, 545, 540, 575]
Amplitude "500/(2*pi)"
Frequency "1/(1000*Ts)"
}
Block {
BlockType Reference
Name "Sine"
Ports [1, 1]
Position [340, 331, 445, 399]
SourceBlock "simulink/Lookup\nTables/Sine"
SourceType "Sine"
ShowPortLabels on
NumDataPoints "(2^8)+1"
}
Block {
BlockType Scope
Name "test\n1"
Ports [4]
Position [635, 104, 695, 251]
Location [1, 45, 1025, 739]
Open off
NumInputPorts "4"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "RC Network Output"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
axes4 "%<SignalLabel>"
}
TimeRange "131072"
YMin "1.5e+006~-2e-009~1.5e+006~-2000"
YMax "3.5e+006~2.5e-010~3.5e+006~2000"
SaveName "ScopeData3"
DataFormat "StructureWithTime"
MaxDataPoints "5000000"
}
Line {
SrcBlock "Add"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Sine"
DstPort 1
}
Branch {
Points [0, -170]
DstBlock "test\n1"
DstPort 3
}
}
Line {
SrcBlock "Sine"
SrcPort 1
DstBlock "Divide2"
DstPort 1
}
Line {
SrcBlock "Divide2"
SrcPort 1
Points [25, 0]
Branch {
Points [0, -145]
DstBlock "test\n1"
DstPort 4
}
Branch {
DstBlock "PN Spectrum1"
DstPort 1
}
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [70, 0; 0, -60]
DstBlock "Divide2"
DstPort 2
}
Line {
SrcBlock "Signal\nGenerator"
SrcPort 1
Points [90, 0]
Branch {
DstBlock "Add"
DstPort 2
}
Branch {
Points [0, -210]
DstBlock "test\n1"
DstPort 2
}
}
Line {
SrcBlock "Ramp"
SrcPort 1
Points [65, 0]
Branch {
Points [0, 100]
DstBlock "Add"
DstPort 1
}
Branch {
Points [0, -130]
DstBlock "test\n1"
DstPort 1
}
}
Annotation {
Name "Demonstration of A/D and Delta-Sigma D/A\nConve"
"rsion"
Position [580, 696]
FontName "Arial"
FontSize 24
}
Annotation {
Name "50kHz\nSample Rate"
Position [332, 759]
}
Annotation {
Name "25kHz\nSample Rate"
Position [487, 754]
}
}
}
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NumRecords 1
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}
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