sig_test.mdl

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      DisplayOption	      "none"
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      OutScaling	      "2^0"
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    Block {
      BlockType		      Scope
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      YMax		      "5"
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      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "0"
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      BlockType		      "S-Function"
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      SFunctionModules	      "''"
      PortCounts	      "[]"
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      Amplitude		      "1"
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      Frequency		      "1"
      Phase		      "0"
      Samples		      "10"
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    Block {
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      SimViewingDevice	      off
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    Block {
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      directory		      "./sysgenADCDACysgen"
      testbench		      on
      simulink_period	      "1"
      sysclk_period	      "6.8"
      incr_netlist	      off
      trim_vbits	      "Everywhere in SubSystem"
      dbl_ovrd		      "According to Block Masks"
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      Name		      "(c) Copyright 1995-2004 Xilinx, Inc.\n#-- All r"
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	Annotation {
	  Name			  "Copyright(C) 2004 by  Xilinx, Inc. All righ"
"ts reserved.\n\nThis file contains proprietary, confidential information of X"
"ilinx, Inc., is distributed under license\nfrom Xilinx, Inc., and may be used"
", copied and/or disclosed only pursuant to the terms of a valid license\nagre"
"ement with Xilinx, Inc. Xilinx hereby grants you a license to use this file s"
"olely for design,\nsimulation, implementation and creation of design files li"
"mited to Xilinx devices or technologies. Use \nwith non-Xilinx devices or tec"
"hnologies is expressly prohibited and immediately terminates your license \nu"
"nless covered by a separate agreement.\n\nXilinx is providing this design, co"
"de, or information \"as-is\" solely for use in developing programs and \nsolu"
"tions for Xilinx devices, with no obligation on the part of Xilinx to provide"
" support. By providing\nthis design, code, or information as one possible imp"
"lementation of this feature, application or standard,\nXilinx is making no re"
"presentation that this implementation is free from any claims of infringement"
". You\nare responsible for obtaining any rights you may require for your impl"
"ementation. Xilinx expressly disclaims\nany warranty whatsoever with respect "
"to the adequacy of the implementation, including but not limited to any\nwarr"
"anties or representations that this implementation is free from claims of inf"
"ringement, implied warranties\nof merchantability or fitness for a particular"
" purpose.\n\nXilinx products are not intended for use in life support applian"
"ces, devices, or systems. Use in such \napplications is expressly prohibited."
"\n\nAny modifications that are made to the Source Code are done at the user's"
" sole risk and will be unsupported. \n\nThis copyright and support notice mus"
"t be retained as part of this text at all times. \n(c) Copyright 1995-2004 Xi"
"linx, Inc. All rights reserved."
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	  Name			  "Demonstration of A/D and Delta-Sigma D/A Co"
"nversion"
	  Position		  [298, 22]
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	  FontWeight		  "bold"
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	  Name			  "This model implements a 14-bit analog to di"
"gital converter (ADC) and a digital to analog converter \n(DAC) for Virtex an"
"d Virtex derivative devices.  The model is based on the delta-sigma DAC and A"
"DC\nimplementations described, respectively, in Xilinx App. Notes 154 and 155"
" by John Logue.  Both\ndocuments can be found at \n\n  http://www.xilinx.com/"
"apps/appsweb.htm\n\nThe ADC requires feedback from the DAC to compute output "
"samples.  The DAC output is a pulse \nstring whose duty cycle is proportional"
" to the amplitude of the desired output voltage.  XAPP154 \ndescribes a low-p"
"ass filter on the DAC output implemented with an RC network.  Here the RC net"
"work\nis simulated using a transfer function block.  XAPP155 specifies an op-"
"amp circuit on the input of\nthe ADC.  In this model, the op-amp is replaced "
"by a relational block.\n\nWhen simulating this model, the behavior is best vi"
"ewed with the simulation duration set to Inf.  The \nDAC input display shows "
"the a binary representation of the DAC input and illustrates the binary searc"
"h\nused by the ADC to constructs a digital sample of the input voltage (in th"
"is case .73).  \n\nThis design occupies 51 slices (26 %) of an xc2s15-6 part "
"and runs at 150 MHz \n(advanced speeds files 1.96, ISE 4.2i software)."
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