iir_filter_config.m

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function iir_filter_config(this_block)

  % Revision History:
  %
  %   05-Nov-2005  (10:12 hours):
  %     Original code was machine generated by Xilinx's System Generator after parsing
  %     E:\project\VTECH\HDL\SPK\COMP\iir_filter.v
  %
  %

  this_block.setTopLevelLanguage('Verilog');

  this_block.setEntityName('iir_filter');

  % System Generator has to assume that your entity  has a combinational feed through; 
  %   if it  doesn't, then comment out the following line:
  this_block.tagAsCombinational;

  this_block.addSimulinkInport('din');
  this_block.addSimulinkInport('fltsel');
  this_block.addSimulinkInport('rstn');

  this_block.addSimulinkOutport('dout');

  dout_port = this_block.port('dout');
  dout_port.setType('UFix_18_0');

  % -----------------------------
  if (this_block.inputTypesKnown)
    % do input type checking, dynamic output type and generic setup in this code block.

    if (this_block.port('din').width ~= 18);
      this_block.setError('Input data type for port "din" must have width=18.');
    end

    if (this_block.port('fltsel').width ~= 1);
      this_block.setError('Input data type for port "fltsel" must have width=1.');
    end

    this_block.port('fltsel').useHDLVector(false);

    if (this_block.port('rstn').width ~= 1);
      this_block.setError('Input data type for port "rstn" must have width=1.');
    end

    this_block.port('rstn').useHDLVector(false);

  end  % if(inputTypesKnown)
  % -----------------------------

  % -----------------------------
   if (this_block.inputRatesKnown)
     % (!) This block is multi-rate
     % (!) Set output rates as appropriate here
     %     Sample commands follow:
           rate_din  = this_block.port('din').rate;
           rate_dout = 2*rate_din; 
           this_block.port('dout').setRate(rate_din);
           this_block.addClkCEPair('clk','ce',rate_din); 
           this_block.addClkCEPair('clk_1','ce_1',rate_dout); 
     %
     %     See the (unused) setup_as_single_rate funciton below for more ideas.
     %
   end  % if(inputRatesKnown)
  % -----------------------------


  % Add addtional source files as needed.
  %  |-------------
  %  | Add files in the order in which they should be compiled.
  %  | If two files "a.vhd" and "b.vhd" contain the entities
  %  | entity_a and entity_b, and entity_a contains a
  %  | component of type entity_b, the correct sequence of
  %  | addFile() calls would be:
  %  |    this_block.addFile('b.vhd');
  %  |    this_block.addFile('a.vhd');
  %  |-------------

  %    this_block.addFile('');
  %    this_block.addFile('');
  this_block.addFile('E:/project/VTECH/HDL/SPK/COMP/iir_filter.v');
  this_block.addFile('E:/project/VTECH/HDL/SPK/COMP/iir_6_filter.v');

return;


% ------------------------------------------------------------

function setup_as_single_rate(block,clkname,cename) 
  inputRates = block.inputRates; 
  uniqueInputRates = unique(inputRates); 
  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
    block.setError('The inputs to this block cannot all be constant.'); 
    return; 
  end 
  if (uniqueInputRates(end) == Inf) 
     hasConstantInput = true; 
     uniqueInputRates = uniqueInputRates(1:end-1); 
  end 
  if (length(uniqueInputRates) ~= 1) 
    block.setError('The inputs to this block must run at a single rate.'); 
    return; 
  end 
  theInputRate = uniqueInputRates(1); 
  for i = 1:block.numSimulinkOutports 
     block.outport(i).setRate(theInputRate); 
  end 
  block.addClkCEPair(clkname,cename,theInputRate); 
  return; 

% ------------------------------------------------------------