hal_intf.h

philips公司ISP1362 USB OTG控制芯片的驱动

/*************************************************************
 * Philips ISP1362 hardware access interface header file
 *
 * (c) 2002 Koninklijke Philips Electronics N.V., All rights reserved
 * 
 * This  source code and any compilation or derivative thereof is the
 * proprietary information of Koninklijke Philips Electronics N.V.
 * and is confidential in nature.
 * Under no circumstances is this software to be exposed to or placed
 * under an Open Source License of any type without the expressed
 * written permission of Koninklijke Philips Electronics N.V.
 *
 * File Name:	hal_intf.h
 *
 * History:	
 *
 *	Version	Date		Author		Comments
 * -------------------------------------------------
 * 	1.0		09/23/02	SYARRA		Initial Creation
 *			04/10/03	SYARRA		corrected register hash def values
 *	1.21	08/04/03	SYARRA		Added isp1362_kernel_user_mesg interface
 *
 * Note: use tab space 4
 *************************************************************/
#ifndef __HAL_INTF_H__
#define __HAL_INTF_H__


/* Values for id_flags filed of isp1362_driver_t */
#define		ISP1362_HC				0		/* Host Controller Driver */
#define		ISP1362_DC				1		/* Device Controller Driver */
#define		ISP1362_OTG				2		/* Otg Controller Driver */
#define		ISP1362_LAST_DEV		(ISP1362_OTG+1)
#define		ISP1362_1ST_DEV			(ISP1362_HC)


/* Registers accessed by Interface functions */
/***** HC Registers *****/
#define		HC_REVISION_REG			0x00	/* Revision Register (read only) */
#define		HC_CONTROL_REG			0x01	/* Control Register */
#define		HC_CMD_STS_REG			0x02	/* Command Status Register */
#define		HC_INT_STS_REG			0x03	/* interrupt status Register 
										   (ohci compatible) */
#define		HC_INT_EN_REG			0x04	/* INterrupt Enable Register */
#define		HC_INT_DIS_REG			0x05	/* Interrupt Disable Register */

#define		HC_FM_INTL_REG			0x0D	/* Frame Interval Register */
#define		HC_FM_REM_REG			0x0E	/* Frame Remaininig Register */
#define		HC_FN_REG				0x0F	/* Frame number register */
#define		HC_LSTH_REG				0x11	/* LS Threshold Register */

#define		HC_RH_DESC_A_REG		0x12	/* Root Hub Descriptor A */
#define		HC_RH_DESC_B_REG		0x13	/* Root Hub Descriptor B */
#define		HC_RH_STATUS_REG		0x14	/* Root Hub Status Register */
#define		HC_RH_PORT1_STS_REG		0x15	/* Root hub port 1 status register */
#define		HC_RH_PORT2_STS_REG		0x12	/* Root hub port 2 status register */

#define 	HC_HW_CNFG_REG			0x20	/* Hardware Configuration
										   register */
#define		HC_DMA_CNFG_REG			0x21	/* DMA configuration register
										   */
#define		HC_TXFR_CNTR_REG		0x22	/* Transfer counter register */
#define		HC_MP_INT_REG			0x24	/* Hw specific interrupt 
										  register */
#define		HC_MP_INT_EN_REG		0x25	/* hw specific Interrupt 
										   Enable Register */
#define		HC_CHIP_ID_REG			0x27	/* Chip Id register (r/w) */
#define		HC_SCRATCH_REG			0x28	/* Scratch Register */
#define		HC_SW_RESET_REG			0xA9	/* Software Reset Register */
#define		HC_BUFF_STS_REG			0x2C	/* Buffer Status Register */
#define		HC_DIR_ADDR_LEN_REG		0x32	/* Direct addr length register */
#define		HC_DIR_ADDR_PORT_REG	0x45	/* Direct addr port register */

#define		HC_ISTL_BUFF_SIZE_REG	0x30	/* ISTL0/ISTL1 buffer size register */
#define		HC_ISTL0_BUFF_PORT_REG	0x40	/* ISTL0 buffer port register */
#define		HC_ISTL1_BUFF_PORT_REG	0x42	/* ISTL1 buffer port register */
#define		HC_ISTL_TOGGLE_RATE_REG	0x47	/* ISTL buffer toggle rate register */

#define		HC_INTL_BUFF_SIZE_REG	0x33	/* INTL buffer size register */
#define		HC_INTL_BUFF_PORT_REG	0x43	/* INTL buffer port register */
#define		HC_INTL_BLK_SIZE_REG	0x53	/* INTL block payload size register */
#define		HC_INTL_DONE_MAP_REG	0x17	/* PTD Done Map register for INTL
											   (Read Only) */
#define		HC_INTL_SKIP_MAP_REG	0x18	/* PTD skip Map register for INTL */

#define		HC_INTL_LAST_PTD_REG	0x19	/* INTL last PTD register */
#define		HC_INTL_CUR_ACT_PTD_REG	0x1A	/* Current Active PTD in INTL List */

#define		HC_ATL_BUFF_SIZE_REG	0x34	/* ATL buffer size register */
#define		HC_ATL_BUFF_PORT_REG	0x44	/* ATL buffer port register */
#define		HC_ATL_BLK_SIZE_REG		0x54	/* ATL block payload size register */
#define		HC_ATL_DONE_MAP_REG		0x1B	/* PTD Done Map register for ATL
											   (Read Only) */
#define		HC_ATL_SKIP_MAP_REG		0x1C	/* PTD skip Map register for ATL */
#define		HC_ATL_LAST_PTD_REG		0x1D	/* ATL last PTD register */
#define		HC_ATL_CUR_ACT_PTD_REG	0x1E	/* Current Active PTD in ATL List */
#define		HC_ATL_THRESHOLD_COUNT_REG		0x51	/* ATL PTD done threshold count register */
#define		HC_ATL_THRESHOLD_TIMEOUT_REG	0x52	/* ATL PTD done threshold timeout register */

/* HC Registers Bit positions definitions */

/* HC_HW_CNFG_REG (16 bit) */
#define 	HC_INT_PIN_ENABLE		0X0001		/* Bit 0    */
#define 	HC_INT_PIN_TRIGGER		0X0002		/* Bit 1    */
#define 	HC_INT_OUTPUT_POLARITY	0X0004		/* Bit 2    */
#define 	HC_DATA_BUS_WIDTH		0X0018		/* Bit 4..3 */
#define		HC_DREQ_OUT_POLARITY	0x0020		/* Bit 5	*/
#define		HC_DACK_IN_POLARITY		0x0040		/* Bit 6	*/
#define		HC_ONE_DMA				0x0080		/* Bit 7	*/
#define		HC_DACK_MODE			0x0100		/* Bit 8	*/
#define		HC_ONE_INT				0x0200		/* Bit 9	*/
#define		HC_ANALOG_OC_ENABLE		0x0400		/* Bit 10 	*/
#define		HC_SUSPEND_CLK_NOT_STOP	0x0800		/* Bit 11 	*/
#define		HC_CONNECT_PLDN_15K_DS1	0x1000		/* Bit 12   */
#define		HC_CONNECT_PLDN_15K_DS2	0x2000		/* Bit 13   */

#define		HC_DATA_BUS_16BIT_WIDTH	0x0008		/* 16 Bit data bus width */



/* HC_MP_INT_REG  */

#define		HC_SOF_INT				0X0001		/* Bit 0: SOF interrupts */
#define		HC_ISTL_0_INT			0X0002		/* Bit 1: ISTL 0 interrupt */
#define		HC_ISTL_1_INT			0X0004		/* Bit 2: ISTL 1 interrupt */
#define		HC_EOT_INT				0X0008		/* Bit 3: End of transfer int.*/
#define		HC_OPR_INT				0X0010		/* Bit 4: HCOR int. */
#define		HC_SUSPEND_INT			0X0020		/* Bit 5 Suspend Interrrupt */
#define		HC_RESUME_INT			0X0040		/* Bit 6 Resume Interrupt */
#define		HC_INTL_INT				0X0080		/* Bit 7: INTL interrupt */
#define		HC_ATL_INT				0X0100		/* Bit 8: ALT interrupt */
#define		HC_OTG_INT				0X0200		/* Bit 9: OTG interrupt */


/***** OTG Registers *****/

#define 	OTG_CONTROL_REG			0x62
#define 	OTG_STATUS_REG			0x67
#define 	OTG_INT_REG				0x68
#define 	OTG_INT_ENABLE_REG		0x69
#define 	OTG_TMR_REG				0x6A
#define 	OTG_ALT_TMR_REG			0x6C

/* OTG_CONTROL_REG */
#define		OTG_DRV_VBUS			0x01
#define		OTG_CHRG_VBUS			0x02
#define		OTG_DISCHRG_VBUS		0x04
#define		OTG_SEL_CP_EXT			0x08
#define		OTG_LOC_CONN			0x10
#define		OTG_A_RDIS_LCON_EN		0x20
#define		OTG_LOC_PULLDN_DP		0x40
#define		OTG_LOC_PULLDN_DM		0x80
#define		OTG_SEL_HC_DC			0x100
#define		OTG_A_SEL_SRP			0x200
#define		OTG_A_SRP_DET_EN		0x400
#define		OTG_B_RCON_LSE0_EN		0x800

/***** DC Registers *****/
#define		DC_READ_EP_REG			0x00	/* Read endpoint buffer */
#define		DC_WRITE_EP_REG			0x10	/* Write Endpoing buffer */
											/* The range 0x00->0x0F &
											 * 0x10->0x1F are allocated
											 * for different endpoints */
#define		DC_RD_EP_CNFG_REG		0x20	/* Read Endpoint Configuration Register
											   the range 0x20->0x2F are for 
											   differnt endpoints (read) */
#define		DC_WR_EP_CNFG_REG		0x30	/* Write endpoint configuration register
											   the range 0x30->0x3F are for
											   differnt endpoints */
#define		DC_EP_STATUS_REG		0x50	/* Read Endpoint Status */
											/* Read only */
											/* The range 0x50->0x5F are
											 * allocated for different eps*/

#define		DC_STALL_EP_REG			0x40	/* Stall endpoint */
											/* 0x40-0x4F are for endpoints 0-15 */
#define		DC_UNSTALL_EP_REG		0x80	/* Stall endpoint */
											/* 0x40-0x4F are for endpoints
											 * 0-15 */
#define		DC_VALIDATE_EP_WR_REG	0x61	/* Validate EP buffer (write) */
#define		DC_VALIDATE_EP_RD_REG	0x6F	/* Validate EP buffer (read) */
#define		DC_CLR_EP_BUFF_REG		0x70	/* Clear endpoint buffers
											   the range 0x70->0x7F (except 0x71)
											   are for different end points */
#define		DC_CHK_EP_STS_REG		0xD0	/* Check endpoint stateus register
											   the range 0xD0->0xDF are for 
											   the differnt end points */

#define		DC_EP_ERR_CODE_REG		0xA0	/* EP end point error code 
											   Register (Read Only) */
											/* The range from A0->AF are 
											 * reserved for different end 
											 * points */

#define		DC_UNLOCK_DEV_REG		0xB0	/* Unlock device Register (write)*/
#define		DC_SCRATCH_REG			0xB3	/* Scratch Register B3 (read)
										 					B2 (write) */
#define		DC_FN_REG				0xB4	/* Frame Number Register (read) */
#define		DC_CHIP_ID_REG			0xB5	/* Chip Id register (read) */
#define		DC_DEV_ADDR_REG			0xB7	/* device address register B7 (read)
										 						   B6 (write) */
#define		DC_MODE_REG				0xB9	/* Mode register B9 (read)
										 				 B8 (write) */
#define		DC_HW_CNFG_REG			0xBB	/* Hardware Configuration
											   register */
#define		DC_INT_REG				0xC0	/* Interrupt status Register */
#define		DC_INT_EN_REG			0xC3	/* Interrupt Enable Register */

#define		DC_DMA_CNFG_REG			0xF1	/* DMA configuration register */
#define		DC_DMA_CNTR_REG			0xF3	/* DMA counter register */
#define		DC_ACK_SETUP_REG		0xF4	/* Acknowledge setup */
#define		DC_SW_RESET_REG			0xF6	/* softwre reset device */

/* DC_HW_CNFG_REG */
#define		DC_INT_POLARITY			0x0001	/* bit 0:Int polarity High */
#define		DC_INT_LEVEL			0x0002	/* bit 1:Int level pulsed */
#define		DC_RWKUPCS				0x0008  /* bit 3:Remote wake up on !CS */
#define		DC_DACK_POLARITY		0x0020	/* bit 5:!DACK polarity High */
#define		DC_DREQ_POLARITY		0x0040	/* bit 6:!DREQ polarity High */
#define		DC_DACK_ONLY			0x0080	/* bit 7: DACK only DMA mode */
#define		DC_CLK_DIV				0x0F00	/* bit 8-11: Clock Division */
#define		DC_CLK_RUN				0x1000	/* bit 12: always run the clock */
#define		DC_NOLAZY_CLK			0x2000	/* bit 13:	No lazy clock */
#define		DC_EXT_PLUP				0x4000	/* bit 14: ext pullup res on D+ */

/* DC_INT_REG &DC_INT_EN_REG */
#define 	DC_RESET_INT			0x00000001	/* bit0: reset interrupt */
#define 	DC_RESUME_INT      		0x00000002	/* bit1: resume interrupt */
#define 	DC_SUSPEND_INT			0x00000004	/* bit2: suspend interrupt */
#define 	DC_EOT_INT 				0x00000008	/* bit3: end of transfer int */
#define 	DC_SOF_INT 				0x00000010  /* bit4: start of frame int */
#define 	DC_PSOF_INT				0x00000020	/* bit5: pseudo sof int */
#define 	DC_SP_EOT_INT			0x00000040	/* bit6: short packet int */
#define		DC_BUS_STS_INT			0x00000080	/* bit7: bus status */
#define 	DC_EPOUT_INT			0x00000100	/* bit8: endpoint 0 out int */
#define 	DC_EPIN_INT				0x00000200  /* bit9: endpoint 0 in int */
#define 	DC_EP1_INT				0x00000400	/* bit10: endpoint 1 int */
#define 	DC_EP2_INT				0x00000800	/* bit11: endpoint 2 int */
#define 	DC_EP3_INT				0x00001000	/* bit12: endpoint 3 int */
#define 	DC_EP4_INT				0x00002000	/* bit13: endpoint 4 int */
#define 	DC_EP5_INT				0x00004000	/* bit14: endpoint 5 int */
#define 	DC_EP6_INT				0x00008000	/* bit15: endpoint 6 int */
#define 	DC_EP7_INT				0x00010000	/* bit16: endpoint 7 int */
#define 	DC_EP8_INT				0x00020000	/* bit17: endpoint 8 int */
#define 	DC_EP9_INT				0x00040000	/* bit18: endpoint 9 int */
#define 	DC_EP10_INT				0x00080000	/* bit19: endpoint 10 int */
#define 	DC_EP11_INT				0x00100000	/* bit20: endpoint 11 int */
#define 	DC_EP12_INT				0x00200000	/* bit21: endpoint 12 int */
#define 	DC_EP13_INT				0x00400000	/* bit22: endpoint 13 int */
#define 	DC_EP14_INT				0x00800000	/* bit23: endpoint 14 int */

/*