otg_fsm.h

philips公司ISP1362 USB OTG控制芯片的驱动

/*******************************************************
 * Philips OTG module for USB OTG controller
 *
 * (c) 2002 Koninklijke Philips Electronics N.V., All rights reserved
 * 
 * This  source code and any compilation or derivative thereof is the
 * proprietary information of Koninklijke Philips Electronics N.V.
 * and is confidential in nature.
 * Under no circumstances is this software to be exposed to or placed
 * under an Open Source License of any type without the expressed
 * written permission of Koninklijke Philips Electronics N.V.
 *
 * File Name:	otg_fsm.h
 *
 * History:	
 *
 *	Version		Date		Author		Comments
 * -------------------------------------------------
 * 	1.0			09/23/02	SYARRA		Initial Creation
 *	1.20		04/01/03	SYARRA		OTG1.0A fixes
 *	1.21		08/04/03	SYARRA		OPT1.2 compliance
 *
 *******************************************************/

#ifndef __OTG_FSM_H__
#define __OTG_FSM_H__

#include "hal_intf.h"

/* OTG timer values in milli seconds */
#define 	A_WAIT_VRISE_TIMER			200
#define 	A_WAIT_BCON_TIMER			1200 
#define 	A_AIDL_BDIS_TIMER			225	/* Minimum 200 msec (OTG1.0A fixes) */
#define 	B_ASE0_BRST_TIMER			4

#define 	B_DATA_PLS_TIMER	  		8		//5-10 msec
#define 	B_VBUS_PLS_TIMER     		15		//10-20 msec

#define		B_BUS_REQ_TIMER				32000	//5-30 sec maximum
#define		A_SUSPEND_DET_TIMER			70
#define		A_BCON_DEBOUNCE_TIMER		120
#define 	B_AIDL_BDIS_TIMER			7	 	/* OTG1.0A fixes */

// Timer Id values 
#define		OTG_INVALID_TIMER_ID		0
#define 	A_WAIT_VRISE_TIMER_ID		1
#define 	A_WAIT_BCON_TIMER_ID		2
#define 	A_AIDL_BDIS_TIMER_ID		3
#define 	B_ASE0_BRST_TIMER_ID		4

#define 	B_DATA_PLS_TIMER_ID			5
#define 	B_VBUS_PLS_TIMER_ID			6

#define		B_BUS_REQ_TIMER_ID			7
#define		A_SUSPEND_DET_TIMER_ID		8
#define		A_BCON_DEBOUNCE_TIMER_ID	9
#define 	B_AIDL_BDIS_TIMER_ID		10	 	/* OTG1.0A fixes */

#define 	OTG_ERR_SRP_FAIL			1
#define 	OTG_ERR_A_WAIT_VRISE_TMOUT	2
#define 	OTG_ERR_A_WAIT_BCON_TMOUT	3
#define 	OTG_ERR_A_AIDL_BDIS_TMOUT	4
#define 	OTG_ERR_B_ASE0_BRST_TMOUT	5
#define 	OTG_ERR_OVERCURRENT			6

#define		IDLE						OTG_IDLE
#define		HOST						OTG_HOST
#define		PERIPHERAL					OTG_PERIPHERAL
#define		BUS_DROP					OTG_BUS_DROP
#define		BUS_OPEN					OTG_BUS_OPEN


/* Complete State values */
#define		A_DEV_BASE					OTG_A_DEV_BASE
#define		B_DEV_BASE					OTG_B_DEV_BASE
#define		WAIT_RMT_CON				OTG_WAIT_RMT_CON
#define		INV_STATE					OTG_INV_STATE

/* Application abstraction states */
#define		A_IDLE						OTG_A_IDLE
#define		A_HOST						OTG_A_HOST
#define		A_PERIPHERAL				OTG_A_PERIPHERAL

#define		B_IDLE						OTG_B_IDLE
#define		B_HOST						OTG_B_HOST
#define		B_PERIPHERAL				OTG_B_PERIPHERAL

/* Additional SW FSM States */
#define		A_WAIT_BCON					OTG_A_WAIT_BCON
#define		A_WAIT_VRISE				OTG_A_WAIT_VRISE
#define		A_SUSPEND					OTG_A_SUSPEND
#define		A_WAIT_VFALL				OTG_A_WAIT_VFALL
#define		A_VBUS_ERR					OTG_A_VBUS_ERR
#define		A_LAST_STATE				OTG_A_LAST_STATE

#define		B_WAIT_ACON					OTG_B_WAIT_ACON
#define		B_SRP_INIT					OTG_B_SRP_INIT
#define		B_LAST_STATE				OTG_B_LAST_STATE


typedef struct otg_tcb {
	__u8	state;
	__u8	app_state;
	__u8	err_code;
	__u8	id:				1;

//for A-device
	__u8   a_vbus_vld:		1;
	__u8	a_sess_vld:		1;
	__u8	a_srp_det:		1;
	__u8	b_conn:			1;
	__u8	b_bus_suspend:	1;
	__u8	b_bus_resume:	1;

	__u8	b_hnp_support:	1;
	__u8	b_srp_support:	1;
	__u8	a_set_b_hnp_en:	1;

	__u8	a_suspend_req:	1;
	__u8	a_clr_err:		1;

//for B-device
	__u8	b_sess_end:		1;
	__u8	b_sess_vld:		1;
	__u8	b_se0_srp:		1;
	__u8	a_conn:			1;
	__u8	a_bus_suspend:	1;
	__u8	a_bus_resume:	1;

	__u8	a_bus_reset:	1;
	__u8	b_srp_done:		1;

	__u8	b_hnp_en:		1;
	__u8	a_hnp_support:	1;
	__u8	a_alt_hnp_support:	1;


//for both A-device and B-device
//	__u8	rmt_conn:		1;
	__u8	bus_req: 		1;
	__u8	bus_drop:		1;

	__u8	b_host_pending: 	1;
	__u8 	AllowStateChange: 	1; // SW permit
	__u8 	Req4StateChange: 	1; // HW indicate

	__u8	TimeOut:  			1;
	__u8	TimerRunning: 		1;
	__u8	TimerId;
	__u16	TimerTick;

//	__u8	UsageBased:		1;
//	__u8	RmtSOF:			1;

}otg_tcb_t;

#define 		FALSE   				0
#define 		TRUE    				(!FALSE)

#define			OTG_START_TIMER			0x80000000

#define 		OTG_IRQ_ID				0x0001
#define 		OTG_IRQ_A_VBUS_VLD		0x0002
#define 		OTG_IRQ_B_SESS_END		0x0004
#define			OTG_IRQ_A_SESS_VLD		0x0008
#define			OTG_IRQ_B_SESS_VLD		0x0010
#define 		OTG_IRQ_RMT_CONN		0x0020
#define 		OTG_IRQ_SUSPEND			0x0040
#define 		OTG_IRQ_RESUME			0x0080
#define 		OTG_IRQ_SRP_DET			0x0100
#define 		OTG_IRQ_SE0_SRP			0x0200
#define 		OTG_IRQ_TMR				0x0400

#define			OTG_IRQ_MASK_ALL			(OTG_IRQ_ID | OTG_IRQ_A_VBUS_VLD | OTG_IRQ_B_SESS_END | OTG_IRQ_A_SESS_VLD | OTG_IRQ_B_SESS_VLD | OTG_IRQ_RMT_CONN | OTG_IRQ_SUSPEND | OTG_IRQ_RESUME | OTG_IRQ_SRP_DET | OTG_IRQ_SE0_SRP | OTG_IRQ_TMR )

#define			OTG_IRQ_MASK			OTG_IRQ_MASK_ALL

// HW supports 0.01 milli second resolution
#define			OTG_TMR_RESOLUTION		100

typedef	struct _bmp_otgctrl {
	__u8		drv_vbus		:1; //b0: drv_vbus
	__u8		chrg_vbus 		:1; //b1: !chrg_vbus
	__u8		dischrg_vbus 	:1; //b2:
	__u8		sel_cp_ext	 	:1; //b3: 0:use CP, 1:use ext 5v
	__u8		loc_conn		:1; //b4: loc_conn(control external 1.5k resistor
	__u8		a_rdis_lcon_en 	:1; //b5:
	__u8		loc_pulldn_dp	:1; //b6
	__u8		loc_pulldn_dm	:1; //b7
	__u8		sel_hc_dc		:1; //b8: 0:atx connect hc, 1:atx connect dc
	__u8		a_sel_srp	 	:1; //b9:
	__u8		a_srp_det_en 	:1; //b10:
	__u8		b_rcon_lse0_en 	:1; //b11:
	__u8		Resrv0			:5; //b12-15
} bmp_otg_ctrl_t;

typedef	union _otg_ctrl {

	bmp_otg_ctrl_t	bitmap;
	__u16			data;
} otg_ctrl_t;

typedef	struct _bmp_otgstatus {
	__u8		ID				:1 ;//b0
	__u8		a_vbus_vld		:1 ;//b1
	__u8		b_sess_end		:1 ;//b2
	__u8		a_sess_vld		:1 ;//b3
	__u8		b_sess_vld		:1 ;//b4
	__u8		rmt_conn		:1 ;//b5
	__u8						:1 ;//b6
	__u8						:1 ;//b7
	__u8						:1 ;//b8
	__u8		b_se0_srp		:1 ;//b9
	__u8						:6 ;//b10-15
} bmp_otg_status_t;

typedef	union _otg_status {

	bmp_otg_status_t	bitmap;
	__u16				data;
} otg_status_t;

typedef	struct _bmp_otgint {
	__u8		ID_c			:1 ;//b0
	__u8		a_vbus_vld_c	:1 ;//b1
	__u8		b_sess_end_c	:1 ;//b2
	__u8		a_sess_vld_c	:1 ;//b3
	__u8		b_sess_vld_c	:1 ;//b4
	__u8		rmt_conn_c		:1 ;//b5
	__u8		bus_suspend		:1 ;//b6
	__u8		bus_resume		:1 ;//b7
	__u8		a_srp_det		:1 ;//b8
	__u8		b_se0_srp		:1 ;//b9
	__u8		otg_tmr_tmout	:1 ;//b10
	__u8						:5 ;//b11-b15
} bmp_interrupt_t;

typedef	union _otg_int {

	bmp_interrupt_t	bitmap;
	__u16			data;
} otg_interrupt_t;

typedef	struct _bmp_otgintie {
	__u8		ID_c			:1 ;//b0
	__u8		a_vbus_vld_IE	:1 ;//b1
	__u8		b_sess_end_IE	:1 ;//b2
	__u8		a_sess_vld_IE	:1 ;//b3
	__u8		b_sess_vld_IE	:1 ;//b4
	__u8		rmt_conn_IE		:1 ;//b5
	__u8		bus_suspend_IE	:1 ;//b6
	__u8		bus_resume_IE	:1 ;//b7
	__u8		a_srp_det_IE	:1 ;//b8
	__u8		b_se0_srp_IE	:1 ;//b9
	__u8		otg_tmr_tmout_IE:1 ;//b10
	__u8						:5 ;//b11-15
} bmp_int_en_t;

typedef	union _otg_ie {

	bmp_int_en_t	bitmap;
	__u16			data;
} otg_int_en_t;

typedef struct _otg_reg {

	// OTG_CONTROL
	otg_ctrl_t 	ctrl_port;

	// OTG_STATUS
	otg_status_t  status_port;

	// OTG_INTERRUPT
	otg_interrupt_t  int_port;

	// OTG_INTERRUPT_ENABLE
	otg_int_en_t  int_en_port;
} otg_reg_t;

typedef struct otg_fsm {
	otg_reg_t			regs;
	otg_tcb_t			tcb;
	void				*hcd_priv;
	void				*dcd_priv;
	void				*usb_otg_data;
	struct isp1362_dev	*dev;
} otg_fsm_t;

#define		otg_fsm_state_change(fsm_data,new_state)			\
			fsm_data->tcb.state = new_state;					\
			fsm_data->tcb.app_state = fsm_state_X_app_state[new_state];	\
			if(fsm_data->usb_otg_data) usb_otgdev_async_notif(fsm_data->usb_otg_data)

extern	void 	otgfsm_run(otg_fsm_t	*fsm_data);
extern	void 	otgfsm_set_state(otg_fsm_t	*fsm_data, __u8	cmd);
extern	void 	otgfsm_status_probe(otg_fsm_t	*fsm_data);
extern	void 	otgfsm_init_fsm_data(otg_fsm_t	*fsm_data);
extern	void 	otgfsm_init(otg_fsm_t	*fsm_data);
extern	void otgfsm_deinit(otg_fsm_t	*fsm_data );
#endif