📄 usb_phci.h
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struct phci *next; // chain of uhci device contexts
int phci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
ed_t * ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t * ed_bulktail; /* last endpoint of bulk list */
ed_t * ed_controltail; /* last endpoint of control list */
ed_t * ed_isohead; /* first endpoint of iso list */
ed_t * ed_isotail; /* last endpoint of iso list */
int intrstatus;
__u32 hc_control; /* copy of the hc control reg */
struct usb_bus * bus;
struct usb_device * dev[128]; /* Usb devices attached to this HCD */
struct virt_root_hub rh; /* Virtual Root Hub information */
unsigned int irq; /* Interrupt line for Philips HC */
unsigned int dma; /* Interrupt line for Philips HC */
__u8 *dma_buff;
__u32 uHcHcdControl_hcd; /* Software Control Register of Philips HC */
/* Bit 5: Bulk List Enable (BLE) */
/* Bit 4: Control List Enable (CLE) */
/* Bit 3: Isochronous Enable (IE) */
/* Bit 2: Periodic List Enable (PLE) */
/* Bit 1..0: Control/Bulk Service Ratio */
__u32 uHcHcdCommandStatus_hcd; /* Software Command Status Register of Philips HC */
/* Bit 1: Control List Filled (CLF) */
/* Bit 2: Bulk List Filled (BLF) */
__u32 hcd_operational_flags; /* Host Controller Driver flags */
/* Bit 0-12: bits of REG_BUFF_STS bits */
/* Bit 16: ISOC scheduling needs to be started */
ed_t * p_int_table[NUM_INTS]; /* Interrupt EndPoint Table (supposdly part of HCCA) */
ed_t * p_ed_bulkhead; /* Bulk ED Head (supposdly part of OHCI register) */
ed_t * p_ed_controlhead; /* Control ED Head (supposdly part of OHCI register) */
#ifdef CONFIG_USB_OTG
phci_otg_data_t *otg; /* OTG module private data */
__u32 otg_port_status; // OTG Port status
struct urb *rh_urb; // Root Hub urb
struct usb_otg_bus *otg_bus; // OTG bus information
#endif /* CONFIG_USB_OTG */
/* PCI device handle and settings */
void *phci_dev; /* Keep name info here */
struct phci_regs phci_regs;
} phci_t;
#define ISOC_TRANSFER_ON 0x00010000 /* Bit 16: ISOC transfer for HCD is started */
#define ISOC_SCHED_TO_START 0x00020000 /* Bit 17: ISOC scheduling needs to be started */
#define ISOC_SCHED_MISSED 0x00040000 /* Bit 18: ISOC scheduling missed needs to be corrected */
#define ISOC_ISTL0_SCHED_TO_START 0x00080000 /* Bit 19: ISOC ISTL0 scheduling needs to be started */
#define ISOC_ISTL1_SCHED_TO_START 0x00100000 /* Bit 20: ISOC ISTL1 scheduling needs to be started */
#define ISOC_ISTL0_ISTL1_TO_START 0x00200000 /* Bit 21: ISO1&ISOC2 both started together */
#define NUM_TDS 0 /* num of preallocated transfer descriptors */
#define NUM_EDS 32 /* num of preallocated endpoint descriptors */
/* Structure for phci related device data structure
* dev->hc_priv
*/
struct phci_device {
ed_t ed[NUM_EDS]; /* Static Ed's */
int ed_cnt; /* total ed's */
wait_queue_head_t * wait; /* Wait queue head */
};
#define phci_to_usb(phci) ((phci)->usb)
#define usb_to_phci(usb) ((struct phci_device *)(usb)->hcpriv)
/*-------------------------------------------------------------------------*/
#define ALLOC_FLAGS (in_interrupt () ? GFP_ATOMIC : GFP_KERNEL)
#ifdef CONFIG_PHCI_MEM_SLAB
#define __alloc(t,c) kmem_cache_alloc(c,ALLOC_FLAGS)
#define __free(c,x) kmem_cache_free(c,x)
static kmem_cache_t *td_cache, *ed_cache;
/*
* WARNING: do NOT use this with "forced slab debug"; it won't respect
* our hardware alignment requirement.
*/
#ifndef PHCI_MEM_FLAGS
#define PHCI_MEM_FLAGS 0
#endif
static int phci_1362_mem_init (void)
{
/* redzoning (or forced debug!) breaks alignment */
int flags = (PHCI_MEM_FLAGS) & ~SLAB_RED_ZONE;
/* TDs accessed by controllers and host */
td_cache = kmem_cache_create ("ohci_td", sizeof (struct td), 0,
flags | SLAB_HWCACHE_ALIGN, NULL, NULL);
if (!td_cache) {
dbg ("no TD cache?");
return -ENOMEM;
}
isp1362_printk("td_cache = %p\n", td_cache);
/* EDs are accessed by controllers and host; dev part is host-only */
ed_cache = kmem_cache_create ("ohci_ed", sizeof (struct phci_device), 0,
flags | SLAB_HWCACHE_ALIGN, NULL, NULL);
if (!ed_cache) {
dbg ("no ED cache?");
kmem_cache_destroy (td_cache);
td_cache = 0;
return -ENOMEM;
}
isp1362_printk("ed_cache = %p\n", ed_cache);
dbg ("slab flags 0x%x", flags);
return 0;
}
static void phci_1362_mem_cleanup (void)
{
if (ed_cache && kmem_cache_destroy (ed_cache))
err ("ed_cache remained");
ed_cache = 0;
if (td_cache && kmem_cache_destroy (td_cache))
err ("td_cache remained");
td_cache = 0;
}
#else
#define __alloc(t,c) kmalloc(sizeof(t),ALLOC_FLAGS)
#define __free(dev,x) kfree(x)
#define td_cache 0
#define ed_cache 0
static inline int phci_1362_mem_init (void) { return 0; }
static inline void phci_1362_mem_cleanup (void) { return; }
/* FIXME: pci_consistent version */
#endif
static inline struct td *
td_alloc (struct phci *hc) {
struct td *td = (struct td *) __alloc (struct td, td_cache);
return td;
}
static inline void
td_free (struct phci *hc, struct td *td) {
__free (td_cache, td);
}
/* DEV + EDs ... only the EDs need to be consistent */
static inline struct phci_device *
dev_alloc (struct phci *hc) {
struct phci_device *dev = (struct phci_device *)
__alloc (struct phci_device, ed_cache);
return dev;
}
static inline void
dev_free (struct phci_device *dev) {
__free (ed_cache, dev);
}
/* Added Philips HC related Constants */
#define YES 1
#define NO 0
#define ON 1
#define OFF 0
#define MAX_GTD 64
#define INVALID_FRAME_NUMBER 0xFFFFFFFF /* valid frame # is 0 - FFFF only */
/* Bit field definition for hwINFO of the td_t */
#define HC_GTD_R 0x00040000UL /* Buffer Rounding */
#define HC_GTD_DP 0x00180000UL /* Direction/PID */
#define HC_GTD_DI 0x00E00000UL /* Delay Interrupt */
#define HC_GTD_T 0x03000000UL /* Data Toggle */
#define HC_GTD_MLSB 0x02000000UL /* Data Toggle MSB */
#define HC_GTD_TLSB 0x01000000UL /* Data Toggle LSB */
#define HC_GTD_EC 0x0C000000UL /* Error Count */
#define HC_GTD_CC 0xF0000000UL /* Condition Code */
/* Bit field definition for hwINFO of the ed_t */
#define HC_ED_FA 0x0000007FUL /* Function Address */
#define HC_ED_EN 0x00000780UL /* Endpoint Number */
#define HC_ED_DIR 0x00001800UL /* Direction of data flow */
#define HC_ED_SPD 0x00002000UL /* Device Speed */
#define HC_ED_SKIP 0x00004000UL /* Skip this ED */
#define HC_ED_F 0x00008000UL /* Format of this ED */
#define HC_ED_MPS 0x07FF0000UL /* Maximum Packet Size */
/* Bit field definition for hwHeadP of the ed_t */
#define HC_ED_TOGGLE 0x00000002UL /* Bit 1, toggle carry */
#define HC_ED_HALTED 0x00000001UL /* Bit 0, halted */
#define OHCI_SETUP 0X00000000UL
#define OHCI_OUT 0x00000001UL
#define OHCI_IN 0x00000002UL
/*-----------------------------------------------------------*/
/* Philips HC control and data port numbers */
/*-----------------------------------------------------------*/
/*-----------------------------------------------------------*/
/* host controller operational registers */
/*-----------------------------------------------------------*/
#define uHcRevision 0x00UL /* Revision Register */
#define uHcControl 0x01UL /* Control Register */
#define uHcCommandStatus 0x02UL /* Command Status Register */
#define uHcInterruptStatus 0x03UL /* Interrupt Status Register */
#define uHcInterruptEnable 0x04UL /* Interrupt Enable Register */
#define uHcInterruptDisable 0x05UL /* Interrupt Disable Register */
#define uHcFmInterval 0x0dUL /* Frame Interval Register */
#define uHcFmRemaining 0x0eUL /* Frame Remaining Register */
#define uHcFmNumber 0x0fUL /* Frame Number Register */
#define uHcLsThreshold 0x11UL /* Threshold register */
#define uHcRhDescriptorA 0x12UL /* Root Hub Descriptor A Register */
#define uHcRhDescriptorB 0x13UL /* Root Hub Descriptor B Register */
#define uHcRhStatus 0x14UL /* Root Hub Status Register */
#define uHcRhPort1Status 0x15UL /* Root Hub Port 1 status */ /* Philips HC has only two root hub ports */
#define uHcRhPort2Status 0x16UL /* Root Hub Port 2 status */
/* These two registers are used internally by software. They are not HC hardware
registers.*/
#define uHcHcdControl 0x17UL /* HCD Software Control Register */
#define uHcHcdCommandStatus 0x18UL /* HCD Software Command Status Register */
/* Bit field definition for register HcCommandStatus */
#define HC_COMMAND_STATUS_HCR 0x00000001UL /* Host Controller Reset */
#define HC_COMMAND_STATUS_CLF 0x00000002UL /* Control List Filled */
#define HC_COMMAND_STATUS_BLF 0x00000004UL /* Bulk List Filled */
/**********************/
/* HcControl Register */
/**********************/
#define CB_RATIO 3 /* Control/Bulk transfer ratio */
/* 0 = 1:1 */
/* 1 = 2:1 */
/* 2 = 3:1 */
/* 3 = 4:1 */
#define PERIODIC_LIST_ENABLE YES /* Periodic transfer enable */
#define ISO_ENABLE YES /* Isochronous transfer enable */
#define CONTROL_LIST_ENABLE YES /* Control transfer enable */
#define BULK_LIST_ENABLE YES /* Bulk transfer enable */
#define HC_STATE 2 /* Host functional state */
/* 0 = Reset */
/* 1 = Resume */
/* 2 = Operational */
/* 3 = Suspend */
#define REMOTE_WAKEUP_CONN NO /* Remote wakeup connected */
#define REMOTE_WAKEUP_ENABLE NO /* Remote wakeup enable */
#define INT_NUM_IRQ0 0x20
/* Bit field definition for register HcControl */
#define HC_CONTROL_HCFS 0x000000C0UL /* Host Controller Functional State, bit 7..6 */
#define HC_CONTROL_RWC 0x00000200UL /* Remote Wakeup Connected, bit 9 */
#define HC_CONTROL_RWE 0x00000400UL /* Remote Wakeup Enable, bit 10 */
/* Bit field definition for HCD register HcHcdControl */
/* PHC does not have this HC register as OHCI */
/* It is added as a global variable to emulate the */
/* OHCI transfer control functionality defined in the */
/* following bit field */
#define HC_CONTROL_CBSR 0x00000003UL /* Control/Bulk ratio */
#define HC_CONTROL_PLE 0X00000004UL /* Periodic List Enable */
#define HC_CONTROL_IE 0x00000008UL /* Isochronous Enable */
#define HC_CONTROL_CLE 0x00000010UL /* Control List Enable */
#define HC_CONTROL_BLE 0x00000020UL /* Bulk List Enable */
#define HC_CONTROL_TIP 0x00000100UL /* Transfer In Progress */
/* Bit field definition for register HcInterruptStatus */
/* HcInterruptEnable/HcInterruptDisable registers */
#define HC_INTERRUPT_SO 0x00000001UL /* Scheduling Overrun */
#define HC_INTERRUPT_SF 0x00000004UL /* Start of Frame */
#define HC_INTERRUPT_RD 0x00000008UL /* Resume Detect */
#define HC_INTERRUPT_UE 0x00000010UL /* Unrecoverable error */
#define HC_INTERRUPT_FNO 0x00000020UL /* Frame Number Overflow */
#define HC_INTERRUPT_RHSC 0x00000040UL /* Root Hub Status Change */
#define HC_INTERRUPT_ATD 0X00000080UL /* ATL List Done */
#define HC_INTERRUPT_MIE 0x80000000UL /* Master Interrupt Enable */
#define HC_INTERRUPT_ALL 0x8000007FUL /* All interrupts */
/****************************/
/* HcRhDescriptorA Register */
/****************************/
#define PORT_POWER_SWITCHING NO /* Must be NO for Philips HC */
#define OVER_CURRENT_PROTECTION YES
#define PER_PORT_OVER_CURRENT_REPORT NO
#define POWER_ON_TO_POWER_GOOD_TIME 50UL /* Max. = 512 Msec. Use even number */
/* Bit field definition for register HcRhDescriptorA */
#define HC_RH_DESCRIPTORA_NDP 0x000000FFUL /* Number of downstream ports */
#define HC_RH_DESCRIPTORA_PSM 0x00000100UL /* Power Switching Mode */
#define HC_RH_DESCRIPTORA_NPS 0x00000200UL /* No Power Switching */
#define HC_RH_DESCRIPTORA_OCPM 0x00000800UL /* OverCurrent Protection Mode */
#define HC_RH_DESCRIPTORA_NOCP 0x00001000UL /* No OverCurrent Protection */
#define HC_RH_DESCRIPTORA_POTPGT 0xFF000000UL /* Power On To Power Good Time */
/****************************/
/* HcRhDescriptorB Register */
/****************************/
#define DEVICE_REMOVABLE 0x00000006UL
#define PORT_POWER_MASK 0x00000000UL
/* Bit field definition for register HcRhDescriptorB */
#define HC_RH_DESCRIPTORB_PPCM 0xFFFF0000UL /* Port Power Control Mask */
#define HC_RH_DESCRIPTORB_DR 0x0000FFFFUL /* Device Removable */
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