dual_bw_eg_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 11:58:26 2004

.cpu_version 0x00000002 16 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:init_all# 5
:init_value# 0
:l000_01# 19
:l000_end# 19
:next_packet# 69
:refcnt_calc_done# 93
:start# 69
:wait_for_packet_data# 70
*-- no_destination 0
;*l0000!msfaddress!!2 gpr_b_rel 08
;*l0000!msfaddress!!3 gpr_b_rel 08
;*l0000!msfaddress!!4 gpr_b_rel 08
;*l0000!msfaddress!!5 gpr_b_rel 08
;*l0000!msfaddress!!6 gpr_b_rel 08
;*l0000!msfaddress!!7 gpr_a_rel 00
;*l0000!msfaddress!!8 gpr_b_rel 08
*l0000!msfaddress gpr_b_rel 08
*l0000!get_ring_num gpr_a_rel 01
*l0000!put_ring_num gpr_b_rel 0C
*@l0000!packet_count gpr_b_abs 00
;*l0000!port_count!!2 gpr_a_rel 02
*l0000!port_count gpr_a_rel 02
*l0000!byte_count gpr_a_rel 03
*l0000!cur_ctx gpr_a_rel 04
;*l0000!txconfigdata0!!2 gpr_b_rel 09
;*l0000!txconfigdata0!!3 gpr_b_rel 09
*l0000!txconfigdata0 gpr_b_rel 09
*$l0000!txconfigdata0 sram_rel 00 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x21
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x21
*l0000!tbuf_element gpr_b_rel 01
*l0000!tbuf_1st_element gpr_b_rel 02
*l0000!tbuf_mask gpr_b_rel 03
;*l0000!dram_addr!!2 gpr_b_rel 04
*l0000!dram_addr gpr_b_rel 04
*l0000!tbuf gpr_a_rel 05
*l0001!temp gpr_b_rel 0E
*$l0002!scratch_base sram_rel 00 0 both 1 0x0
*$l0002!scratch_head sram_rel 01 0 both 1 0x0
*$l0002!scratch_tail sram_rel 02 0 both 1 0x0
*$l0003!packet_info sram_rel 00 0 both 1 0x0
*l0003!mask gpr_b_rel 0D
;*l0004!tmp_addr!!2 gpr_b_rel 0A
*l0004!tmp_addr gpr_b_rel 0A
*$l0004!tmp_data sram_rel 00 0 both 1 0x0
;*l0005!tbuf_addr!!2 gpr_b_rel 05
;*l0005!tbuf_addr!!3 gpr_a_rel 06
*l0005!tbuf_addr gpr_b_rel 05
;*l0005!refcnt!!2 gpr_b_rel 06
;*l0005!refcnt!!3 gpr_b_rel 06
*l0005!refcnt gpr_b_rel 06
;*l0006!tmp_addr!!2 gpr_b_rel 07
*l0006!tmp_addr gpr_b_rel 07
*$l0006!tmp_data sram_rel 00 0 both 1 0x0
*l0007!temp gpr_b_rel 0B
*l0006!tmp_scratch_sig signal 01 0
*l0004!tmp_scratch_sig signal 01 0
*l0004!tmp_scratch_sig!!2 signal 01 0
*l0003!scratch_sig signal 01 0
*l0002!scratch_sig3 signal 03 0
*l0002!scratch_sig3!!5 signal 03 0
*l0002!scratch_sig3!!4 signal 03 0
*l0002!scratch_sig3!!3 signal 03 0
*l0002!scratch_sig3!!2 signal 03 0
*l0002!scratch_sig2 signal 02 0
*l0002!scratch_sig2!!5 signal 02 0
*l0002!scratch_sig2!!4 signal 02 0
*l0002!scratch_sig2!!3 signal 02 0
*l0002!scratch_sig2!!2 signal 02 0
*l0002!scratch_sig1 signal 01 0
*l0002!scratch_sig1!!5 signal 01 0
*l0002!scratch_sig1!!4 signal 01 0
*l0002!scratch_sig1!!3 signal 01 0
*l0002!scratch_sig1!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!dram_sig signal 02 0
.%type R
.%type SI
.%scope global
.%var l0007!temp 0 R
.%liverange 0 B11 105:109
.%liverange 0 ~B11 69:104
.%var $l0006!tmp_data 0 R
.%liverange 0 $W0 100:105
.%liverange 0 $R0 110:110
.%var l0006!tmp_addr 0 R
.%liverange 0 B7 98:109
.%liverange 0 ~B7 69:97
.%var l0005!refcnt 0 R
.%liverange 0 B6 90:109
.%liverange 0 ~B6 69:89
.%var l0005!tbuf_addr 0 R
.%liverange 0 B5 86:87
.%liverange 0 A6 88:109
.%liverange 0 ~A6 69:85
.%var $l0004!tmp_data 0 R
.%liverange 0 $W0 79:99
.%liverange 0 $R0 110:110
.%var l0004!tmp_addr 0 R
.%liverange 0 B10 77:109
.%liverange 0 ~B10 69:76
.%var l0003!mask 0 R
.%liverange 0 B13 70:109
.%liverange 0 ~B13 69:69
.%var $l0003!packet_info 0 R
.%liverange 0 $W0 110:110
.%liverange 0 $R0 71:109
.%liverange 0 ~$R0 69:70
.%var $l0002!scratch_tail 0 R
.%liverange 0 $W2 41:68
.%liverange 0 ~$W2 69:109
.%liverange 0 $R2 110:110
.%var $l0002!scratch_head 0 R
.%liverange 0 $W1 40:68
.%liverange 0 ~$W1 69:106
.%liverange 0 $R1 110:110
.%var $l0002!scratch_base 0 R
.%liverange 0 $W0 42:68
.%liverange 0 ~$W0 69:78
.%liverange 0 $R0 110:110
.%var l0001!temp 0 R
.%liverange 0 B14 7:109
.%var l0000!tbuf 0 R
.%liverange 0 A5 9:109
.%var l0000!dram_addr 0 R
.%liverange 0 B4 74:109
.%liverange 0 ~B4 69:73
.%var l0000!tbuf_mask 0 R
.%liverange 0 B3 10:109
.%var l0000!tbuf_1st_element 0 R
.%liverange 0 B2 13:109
.%var l0000!tbuf_element 0 R
.%liverange 0 B1 83:109
.%liverange 0 ~B1 69:82
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 107:109
.%liverange 0 ~$W1 69:106
.%liverange 0 $R1 110:110
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 106:109
.%liverange 0 ~$W0 69:78
.%liverange 0 $R0 110:110
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W0 23:41
.%liverange 0 $R0 110:110
.%var l0000!txconfigdata0 0 R
.%liverange 0 B9 21:68
.%liverange 0 ~B9 69:109
.%var l0000!cur_ctx 0 R
.%liverange 0 A4 8:109
.%var l0000!byte_count 0 R
.%liverange 0 A3 72:109
.%liverange 0 ~A3 69:71
.%var l0000!port_count 0 R
.%liverange 0 A2 12:109
.%var @l0000!packet_count 0 R
.%liverange 0 @B0 0:109
.%var l0000!put_ring_num 0 R
.%liverange 0 B12 15:109
.%var l0000!get_ring_num 0 R
.%liverange 0 A1 14:109
.%var l0000!msfaddress 0 R
.%liverange 0 B8 20:68 104:109
.%liverange 0 ~B8 69:102
.%liverange 0 A0 103:103
.%var l0006!tmp_scratch_sig 1 R
.%liverange 0 G1 101:101
.%var l0004!tmp_scratch_sig 1 R
.%liverange 0 G1 80:80 82:82
.%var l0003!scratch_sig 1 R
.%liverange 0 G1 71:71
.%var l0002!scratch_sig3 1 R
.%liverange 0 G3 45:46 50:51 55:56 60:61 65:66
.%var l0002!scratch_sig2 1 R
.%liverange 0 G2 44:46 49:51 54:56 59:61 64:66
.%var l0002!scratch_sig1 1 R
.%liverange 0 G1 43:46 48:51 53:56 58:61 63:66
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:3 5:18
.%var l0000!msf_sig 1 R
.%liverange 0 G1 24:24 28:28 30:30 32:32 34:34 39:39 108:108
.%var l0000!dram_sig 1 R
.%liverange 0 D2 97:102
.%scope end
.0 D801400010 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 59 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.reg l0000!msfaddress l0000!msfaddress0 l0000!msfaddress1
	.%line 60 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.reg l0000!pci_base l0000!get_ring_num l0000!put_ring_num @l0000!packet_count
	.%line 61 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.reg l0000!port_count
	.%line 62 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.reg l0000!byte_count l0000!cur_ctx
	.%line 63 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.reg l0000!txconfigdata0
	.%line 64 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.reg $l0000!txconfigdata0
	.%line 65 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 66 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.reg l0000!tbuf_element l0000!tbuf_1st_element l0000!tbuf_mask
	.%line 67 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.reg l0000!dram_addr l0000!tbuf
	.%line 68 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.sig l0000!dram_sig l0000!msf_sig l0000!interthd_sig
	.%line 70 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.xfer_order $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 72 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.addr l0000!interthd_sig 15
	.%line 73 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
	.set_sig l0000!interthd_sig
	.%line 75 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0 5
	init_value#:
	.%line 76 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0 5
		br=ctx[0, init_all#]
.1 D801404010 common_code
	.%line 77 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0 5
		br=ctx[1, init_all#]
.2 D801408010 common_code
	.%line 78 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0 5
		br=ctx[2, init_all#]
.3 D80140C010 common_code
	.%line 79 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0 5
		br=ctx[3, init_all#]
.4 E000010000 common_code
	.%line 80 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		ctx_arb[kill], any
.5 FC044C0000 common_code
	.%line 83 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		.local l0001!temp
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 1
	init_all#:
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 1
		local_csr_rd[active_ctx_sts]
.6 F000003B00 common_code
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 0
		immed[l0001!temp, 0]
.7 A400403B07 common_code
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		alu[l0000!cur_ctx, 0x7, and, l0001!temp]
.8 F0020C0005 common_code
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		.endlocal
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		immed[l0000!tbuf, 0x2000]
.9 F000000F0F common_code
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		immed[l0000!tbuf_mask, 15]
.10 F000020300 common_code
	.%line 91 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		immed[@l0000!packet_count, 0]
.11 F0000C0002 common_code
	.%line 92 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		immed[l0000!port_count, 0]
.12 91C0280204 common_code
	.%line 94 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		alu_shf[l0000!tbuf_1st_element, --, b, l0000!cur_ctx, <<4]
.13 81E0180204 common_code
	.%line 95 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		alu_shf[l0000!get_ring_num , --, b, l0000!cur_ctx, <<2]
.14 91E0C09200 common_code
	.%line 96 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		alu_shf[l0000!put_ring_num , --, b, 4, <<2]
.15 A0700C0004 common_code
	.%line 98 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		.if (cur_ctx > 0)
	.%line 98 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		alu[--,--,b,l0000!cur_ctx]
.16 D804C0010A common_code
	.%line 98 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0 19
		ble[l000_01#]
.17 E000008000 common_code
	.%line 99 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
			ctx_arb[l0000!interthd_sig]
.18 D811400018 common_code
	.%line 100 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0 69
			br[start#]
.19 F000002304 common_code
	.%line 101 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		.endif
	.%line 101 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		l000_01#: 
		l000_end#: 
	.%line 110 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		immed[l0000!msfaddress, 0x0004]
.20 F000002704 common_code
	.%line 111 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		immed[l0000!txconfigdata0, 4]
.21 F440F02720 common_code
	.%line 112 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		immed_w1[l0000!txconfigdata0, 3872]
.22 A018002400 common_code
	.%line 113 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		alu[$l0000!txconfigdata0, --, b, l0000!txconfigdata0]
.23 3D10002020 common_code
	.%line 114 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0
		msf[write, $l0000!txconfigdata0, 0, l0000!msfaddress, 1], ctx_swap[l0000!msf_sig]
.24 F00000271D common_code
	.%line 121 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_tx.uc" 1 0