dual_bw_eg_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 11:58:26 2004

.cpu_version 0x00000002 16 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:cont_init1# 13
:cont_init2# 33
:init_rbuf# 40
:init_value# 0
:not_ctx_0# 3
:not_ctx_1# 6
:not_ctx_2# 9
:not_ctx_3# 12
:receivepacket# 63
:rsw# 65
:set_refcnt_overwrite_bit# 73
*-- no_destination 0
*$l0000!transferreg00 sram_rel 00 0 both 2 0x32
*$l0000!transferreg01 sram_rel 01 0 both 1 0x32
;*l0000!rxthreadlist!!2 gpr_b_rel 05
;*l0000!rxthreadlist!!3 gpr_b_rel 05
*l0000!rxthreadlist gpr_a_rel 07
*l0000!bytecnt gpr_a_rel 00
*l0000!elem gpr_a_rel 01
*l0000!error gpr_b_rel 0A
*l0000!rx_channel_num gpr_b_rel 00
*l0000!cur_ctx gpr_a_rel 06
*@l0000!packet_count gpr_b_abs 01
;*l0000!rxconfigdata!!2 gpr_a_rel 02
*l0000!rxconfigdata gpr_b_rel 06
*l0000!rbuf gpr_a_rel 03
*l0000!ring_num gpr_b_rel 00
;*l0000!msfaddress!!2 gpr_b_rel 0B
;*l0000!msfaddress!!3 gpr_b_rel 0B
;*l0000!msfaddress!!4 gpr_b_rel 0B
;*l0000!msfaddress!!5 gpr_b_rel 0B
;*l0000!msfaddress!!6 gpr_b_rel 0B
*l0000!msfaddress gpr_b_rel 0B
*l0000!threadfreelist_addr gpr_b_rel 02
*l0000!elementdone_addr gpr_a_rel 04
;*l0000!drampacketbase!!2 gpr_b_rel 03
*l0000!drampacketbase gpr_b_rel 03
*l0000!put_ring_num gpr_b_rel 04
*l0000!rx_count_ring_num gpr_b_rel 04
*l0001!temp gpr_b_rel 03
*l0001!cur_me gpr_b_rel 0F
*l0002!rxconfigdata0 gpr_b_rel 0C
*$l0002!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0003!temp_reg gpr_b_rel 05
*l0003!temp gpr_b_rel 06
*l0004!rxupcontrol gpr_b_rel 0D
*$l0004!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0005!rxconfigdata0 gpr_b_rel 0E
*$l0005!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0006!rbufoffset gpr_b_rel 07
;*l0006!refcnt!!2 gpr_a_rel 05
*l0006!refcnt gpr_b_rel 08
;*l0006!temp!!2 gpr_b_rel 09
;*l0006!temp!!3 gpr_b_rel 09
*l0006!temp gpr_b_rel 09
*$l0007!temp0 sram_rel 00 0 both 1 0x0
*$l0008!scratch_packet_count sram_rel 00 0 both 1 0x0
*l0008!scratch_sig signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig_thd signal 01 0
*l0000!sig_dram_xfer1 signal 02 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var $l0008!scratch_packet_count 0 R
.%liverange 0 $W0 84:85
.%liverange 0 ~$W0 63:80
.%liverange 0 $R0 86:86
.%var $l0007!temp0 0 R
.%liverange 0 $W0 81:83
.%liverange 0 $R0 86:86
.%var l0006!temp 0 R
.%liverange 0 B9 76:85
.%liverange 0 ~B9 63:75
.%var l0006!refcnt 0 R
.%liverange 0 B8 70:73
.%liverange 0 A5 74:85
.%liverange 0 ~A5 63:69
.%var l0006!rbufoffset 0 R
.%liverange 0 B7 75:85
.%liverange 0 ~B7 63:74
.%var $l0005!rxconfigdata0 0 R
.%liverange 0 $W0 58:62
.%liverange 0 ~$W0 63:80
.%liverange 0 $R0 86:86
.%var l0005!rxconfigdata0 0 R
.%liverange 0 B14 56:62
.%liverange 0 ~B14 63:85
.%var $l0004!rxconfigdata0 0 R
.%liverange 0 $W0 47:57
.%liverange 0 $R0 86:86
.%var l0004!rxupcontrol 0 R
.%liverange 0 B13 46:62
.%liverange 0 ~B13 63:85
.%var l0003!temp 0 R
.%liverange 0 B6 41:62
.%liverange 0 ~B6 40:40 63:85
.%var l0003!temp_reg 0 R
.%liverange 0 B5 40:62
.%liverange 0 ~B5 63:85
.%var $l0002!rxconfigdata0 0 R
.%liverange 0 $W0 37:46
.%liverange 0 $R0 86:86
.%var l0002!rxconfigdata0 0 R
.%liverange 0 B12 35:62
.%liverange 0 ~B12 63:85
.%var l0001!cur_me 0 R
.%liverange 0 B15 16:85
.%var l0001!temp 0 R
.%liverange 0 B3 15:23
.%var l0000!rx_count_ring_num 0 R
.%liverange 0 B4 28:85
.%var l0000!put_ring_num 0 R
.%liverange 0 B4 27:27
.%var l0000!drampacketbase 0 R
.%liverange 0 B3 24:85
.%var l0000!elementdone_addr 0 R
.%liverange 0 A4 29:85
.%var l0000!threadfreelist_addr 0 R
.%liverange 0 B2 2:2 5:5 8:8 11:11 13:85
.%var l0000!msfaddress 0 R
.%liverange 0 B11 38:62
.%liverange 0 ~B11 63:85
.%var l0000!ring_num 0 R
.%liverange 0 B0 18:62
.%liverange 0 ~B0 63:68
.%var l0000!rbuf 0 R
.%liverange 0 A3 30:85
.%var l0000!rxconfigdata 0 R
.%liverange 0 B6 22:22
.%liverange 0 A2 23:85
.%var @l0000!packet_count 0 R
.%liverange 0 @B1 0:85
.%var l0000!cur_ctx 0 R
.%liverange 0 A6 17:85
.%var l0000!rx_channel_num 0 R
.%liverange 0 B0 69:85
.%liverange 0 ~B0 63:68
.%var l0000!error 0 R
.%liverange 0 B10 68:85
.%liverange 0 ~B10 63:67
.%var l0000!elem 0 R
.%liverange 0 A1 66:85
.%liverange 0 ~A1 63:65
.%var l0000!bytecnt 0 R
.%liverange 0 A0 67:85
.%liverange 0 ~A0 63:66
.%var l0000!rxthreadlist 0 R
.%liverange 0 A7 19:19
.%liverange 0 B5 20:39
.%liverange 0 ~B5 63:85
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 86:86
.%liverange 0 $R1 86:86
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:36
.%liverange 0 ~$W0 63:80
.%liverange 0 $R0 0:85
.%var l0008!scratch_sig 1 R
.%liverange 0 G1 85:85
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:11 13:32
.%var l0000!rx_sig_thd 1 R
.%liverange 0 G1 63:65
.%var l0000!sig_dram_xfer1 1 R
.%liverange 0 D2 79:80
.%var l0000!msf_sig 1 R
.%liverange 0 G1 39:39 49:49 51:51 53:53 55:55 60:60 82:82
.%scope end
.0 D800C00011 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 60 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.reg $l0000!transferreg00 $l0000!transferreg01
	.%line 61 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.reg l0000!rxthreadlist l0000!bytecnt l0000!elem l0000!error l0000!rx_channel_num
	.%line 62 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.reg l0000!cur_ctx
	.%line 63 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.reg @l0000!packet_count
	.%line 64 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.reg l0000!rxconfigdata
	.%line 65 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.reg l0000!rbuf l0000!ring_num
	.%line 66 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.reg l0000!msfaddress l0000!threadfreelist_addr l0000!elementdone_addr
	.%line 67 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.reg l0000!drampacketbase
	.%line 68 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.reg l0000!put_ring_num l0000!rx_count_ring_num
	.%line 69 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.sig l0000!msf_sig l0000!sig_dram_xfer1
	.%line 70 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.sig l0000!rx_sig_thd l0000!interthd_sig
	.%line 71 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.xfer_order $l0000!transferreg00 $l0000!transferreg01
	.%line 73 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.addr l0000!interthd_sig 15
	.%line 75 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.set $l0000!transferreg00
	.%line 76 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.set_sig l0000!interthd_sig
	.%line 78 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 3
	init_value#:
	.%line 79 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 3
		br!=ctx[0, not_ctx_0#]
.1 F000000B30 common_code
	.%line 80 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
		immed[l0000!threadfreelist_addr, 0x0030]
.2 D803400018 common_code
	.%line 81 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 13
		br[cont_init1#]
.3 D801804011 common_code
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 6
	not_ctx_0#:
	.%line 83 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 6
		br!=ctx[1, not_ctx_1#]
.4 F000000B34 common_code
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
		immed[l0000!threadfreelist_addr, 0x0034]
.5 D803400018 common_code
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 13
		br[cont_init1#]
.6 D802408011 common_code
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 9
	not_ctx_1#:
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 9
		br!=ctx[2, not_ctx_2#]
.7 F000000B38 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
		immed[l0000!threadfreelist_addr, 0x0038]
.8 D803400018 common_code
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 13
		br[cont_init1#]
.9 D80300C011 common_code
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 12
	not_ctx_2#:
	.%line 91 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 12
		br!=ctx[3, not_ctx_3#]
.10 F000000B3C common_code
	.%line 92 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
		immed[l0000!threadfreelist_addr, 0x003c]
.11 D803400018 common_code
	.%line 93 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0 13
		br[cont_init1#]
.12 E000010000 common_code
	.%line 94 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	not_ctx_3#:
	.%line 95 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
		ctx_arb[kill], any
.13 FC044C0000 common_code
	.%line 98 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
	.begin
	.%line 99 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 0
		.reg l0001!temp l0001!cur_me
	.%line 97 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 1
	cont_init1#:
	.%line 100 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 1 1
		local_csr_rd[active_ctx_sts]
.14 F000000F00 common_code
	.%line 101 "C:\phase9rel\diag\test_suites\microcode\dual_bw_loopback\dual_bw_rx.uc" 0
		immed[l0001!temp, 0]
.15 9430F00D2F common_code