me_register_test.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Mon Mar 01 17:17:19 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:dram_xfer_reg_cont0# 132
:dram_xfer_reg_cont1# 140
:dram_xfer_reg_cont10# 212
:dram_xfer_reg_cont11# 220
:dram_xfer_reg_cont12# 228
:dram_xfer_reg_cont13# 236
:dram_xfer_reg_cont14# 244
:dram_xfer_reg_cont15# 252
:dram_xfer_reg_cont2# 148
:dram_xfer_reg_cont3# 156
:dram_xfer_reg_cont4# 164
:dram_xfer_reg_cont5# 172
:dram_xfer_reg_cont6# 180
:dram_xfer_reg_cont7# 188
:dram_xfer_reg_cont8# 196
:dram_xfer_reg_cont9# 204
:dram_xfer_reg_error0# 285
:dram_xfer_reg_error1# 287
:dram_xfer_reg_error10# 305
:dram_xfer_reg_error11# 307
:dram_xfer_reg_error12# 309
:dram_xfer_reg_error13# 311
:dram_xfer_reg_error14# 313
:dram_xfer_reg_error15# 315
:dram_xfer_reg_error2# 289
:dram_xfer_reg_error3# 291
:dram_xfer_reg_error4# 293
:dram_xfer_reg_error5# 295
:dram_xfer_reg_error6# 297
:dram_xfer_reg_error7# 299
:dram_xfer_reg_error8# 301
:dram_xfer_reg_error9# 303
:end# 3579
:gpr_0_cont# 369
:gpr_0_error# 463
:gpr_10_cont# 429
:gpr_10_error# 483
:gpr_11_cont# 435
:gpr_11_error# 485
:gpr_12_cont# 441
:gpr_12_error# 487
:gpr_13_cont# 447
:gpr_13_error# 489
:gpr_14_cont# 453
:gpr_14_error# 491
:gpr_15_cont# 462
:gpr_15_error# 493
:gpr_1_cont# 375
:gpr_1_error# 465
:gpr_2_cont# 381
:gpr_2_error# 467
:gpr_3_cont# 387
:gpr_3_error# 469
:gpr_4_cont# 393
:gpr_4_error# 471
:gpr_5_cont# 399
:gpr_5_error# 473
:gpr_6_cont# 405
:gpr_6_error# 475
:gpr_7_cont# 411
:gpr_7_error# 477
:gpr_8_cont# 417
:gpr_8_error# 479
:gpr_9_cont# 423
:gpr_9_error# 481
:gpr_test# 332
:gpr_test_write_status# 495
:local_memory_error# 2467
:local_memory_test# 515
:me0__0# 3301
:me0__1# 3571
:me0_me3_0# 108
:me0_me3_1# 327
:me0_me3_2# 508
:me3_me7# 3564
:me7# 3567
:me_obtain0# 109
:me_obtain1# 328
:me_obtain2# 509
:next_neighbor_reg_internal_error# 2745
:next_neighbor_reg_test# 2474
:nn_ext_write_status_to_scratch# 3572
:sram_xfer_reg_cont0# 128
:sram_xfer_reg_cont1# 136
:sram_xfer_reg_cont10# 208
:sram_xfer_reg_cont11# 216
:sram_xfer_reg_cont12# 224
:sram_xfer_reg_cont13# 232
:sram_xfer_reg_cont14# 240
:sram_xfer_reg_cont15# 248
:sram_xfer_reg_cont2# 144
:sram_xfer_reg_cont3# 152
:sram_xfer_reg_cont4# 160
:sram_xfer_reg_cont5# 168
:sram_xfer_reg_cont6# 176
:sram_xfer_reg_cont7# 184
:sram_xfer_reg_cont8# 192
:sram_xfer_reg_cont9# 200
:sram_xfer_reg_error0# 253
:sram_xfer_reg_error1# 255
:sram_xfer_reg_error10# 273
:sram_xfer_reg_error11# 275
:sram_xfer_reg_error12# 277
:sram_xfer_reg_error13# 279
:sram_xfer_reg_error14# 281
:sram_xfer_reg_error15# 283
:sram_xfer_reg_error2# 257
:sram_xfer_reg_error3# 259
:sram_xfer_reg_error4# 261
:sram_xfer_reg_error5# 263
:sram_xfer_reg_error6# 265
:sram_xfer_reg_error7# 267
:sram_xfer_reg_error8# 269
:sram_xfer_reg_error9# 271
:transfer_reg_test# 0
:xfer_reg_test_write_status# 317
*-- no_destination 0
*l0000!a0 gpr_a_rel 00
*l0000!a1 gpr_a_rel 01
*l0000!a2 gpr_a_rel 02
*l0000!a3 gpr_a_rel 03
*l0000!a4 gpr_a_rel 04
*l0000!a5 gpr_a_rel 05
*l0000!a6 gpr_a_rel 06
*l0000!a7 gpr_a_rel 07
*l0000!a8 gpr_a_rel 08
*l0000!a9 gpr_a_rel 09
*l0000!a10 gpr_a_rel 0A
*l0000!a11 gpr_a_rel 0B
*l0000!a12 gpr_a_rel 0C
*l0000!a13 gpr_a_rel 0D
*l0000!a14 gpr_a_rel 0E
*l0000!a15 gpr_a_rel 0F
*l0000!b0 gpr_b_rel 00
*l0000!b1 gpr_b_rel 01
*l0000!b2 gpr_b_rel 02
*l0000!b3 gpr_b_rel 03
*l0000!b4 gpr_b_rel 04
*l0000!b5 gpr_b_rel 05
*l0000!b6 gpr_b_rel 06
*l0000!b7 gpr_b_rel 07
*l0000!b8 gpr_b_rel 08
*l0000!b9 gpr_b_rel 09
*l0000!b10 gpr_b_rel 0A
*l0000!b11 gpr_b_rel 0B
*l0000!b12 gpr_b_rel 0C
*l0000!b13 gpr_b_rel 0D
*l0000!b14 gpr_b_rel 0E
*l0000!b15 gpr_b_rel 0F
*$l0000!sw0 sram_rel 00 0 both 16 0x62
*$l0000!sw1 sram_rel 01 0 both 15 0x62
*$l0000!sw2 sram_rel 02 0 both 14 0x62
*$l0000!sw3 sram_rel 03 0 both 13 0x62
*$l0000!sw4 sram_rel 04 0 both 12 0x62
*$l0000!sw5 sram_rel 05 0 both 11 0x62
*$l0000!sw6 sram_rel 06 0 both 10 0x62
*$l0000!sw7 sram_rel 07 0 both 9 0x62
*$l0000!sw8 sram_rel 08 0 both 8 0x62
*$l0000!sw9 sram_rel 09 0 both 7 0x62
*$l0000!sw10 sram_rel 0A 0 both 6 0x62
*$l0000!sw11 sram_rel 0B 0 both 5 0x62
*$l0000!sw12 sram_rel 0C 0 both 4 0x62
*$l0000!sw13 sram_rel 0D 0 both 3 0x62
*$l0000!sw14 sram_rel 0E 0 both 2 0x62
*$l0000!sw15 sram_rel 0F 0 both 1 0x62
*$l0000!sr0 sram_rel 00 0 both 16 0x42
*$l0000!sr1 sram_rel 01 0 both 15 0x42
*$l0000!sr2 sram_rel 02 0 both 14 0x42
*$l0000!sr3 sram_rel 03 0 both 13 0x42
*$l0000!sr4 sram_rel 04 0 both 12 0x42
*$l0000!sr5 sram_rel 05 0 both 11 0x42
*$l0000!sr6 sram_rel 06 0 both 10 0x42
*$l0000!sr7 sram_rel 07 0 both 9 0x42
*$l0000!sr8 sram_rel 08 0 both 8 0x42
*$l0000!sr9 sram_rel 09 0 both 7 0x42
*$l0000!sr10 sram_rel 0A 0 both 6 0x42
*$l0000!sr11 sram_rel 0B 0 both 5 0x42
*$l0000!sr12 sram_rel 0C 0 both 4 0x42
*$l0000!sr13 sram_rel 0D 0 both 3 0x42
*$l0000!sr14 sram_rel 0E 0 both 2 0x42
*$l0000!sr15 sram_rel 0F 0 both 1 0x42
*$$l0000!dw0 dram_rel 00 0 both 16 0x22
*$$l0000!dw1 dram_rel 01 0 both 15 0x22
*$$l0000!dw2 dram_rel 02 0 both 14 0x22
*$$l0000!dw3 dram_rel 03 0 both 13 0x22
*$$l0000!dw4 dram_rel 04 0 both 12 0x22
*$$l0000!dw5 dram_rel 05 0 both 11 0x22
*$$l0000!dw6 dram_rel 06 0 both 10 0x22
*$$l0000!dw7 dram_rel 07 0 both 9 0x22
*$$l0000!dw8 dram_rel 08 0 both 8 0x22
*$$l0000!dw9 dram_rel 09 0 both 7 0x22
*$$l0000!dw10 dram_rel 0A 0 both 6 0x22
*$$l0000!dw11 dram_rel 0B 0 both 5 0x22
*$$l0000!dw12 dram_rel 0C 0 both 4 0x22
*$$l0000!dw13 dram_rel 0D 0 both 3 0x22
*$$l0000!dw14 dram_rel 0E 0 both 2 0x22
*$$l0000!dw15 dram_rel 0F 0 both 1 0x22
*$$l0000!dr0 dram_rel 00 0 both 16 0x2
*$$l0000!dr1 dram_rel 01 0 both 15 0x2
*$$l0000!dr2 dram_rel 02 0 both 14 0x2
*$$l0000!dr3 dram_rel 03 0 both 13 0x2
*$$l0000!dr4 dram_rel 04 0 both 12 0x2
*$$l0000!dr5 dram_rel 05 0 both 11 0x2
*$$l0000!dr6 dram_rel 06 0 both 10 0x2
*$$l0000!dr7 dram_rel 07 0 both 9 0x2
*$$l0000!dr8 dram_rel 08 0 both 8 0x2
*$$l0000!dr9 dram_rel 09 0 both 7 0x2
*$$l0000!dr10 dram_rel 0A 0 both 6 0x2
*$$l0000!dr11 dram_rel 0B 0 both 5 0x2
*$$l0000!dr12 dram_rel 0C 0 both 4 0x2
*$$l0000!dr13 dram_rel 0D 0 both 3 0x2
*$$l0000!dr14 dram_rel 0E 0 both 2 0x2
*$$l0000!dr15 dram_rel 0F 0 both 1 0x2
*l0000!signal1 signal 01 0
*l0000!scratch_write signal 01 0
*l0000!scratch_write!!5 signal 01 0
*l0000!scratch_write!!4 signal 01 0
*l0000!scratch_write!!3 signal 01 0
*l0000!scratch_write!!2 signal 01 0
*l0000!sram_read signal 01 0
*l0000!sram_write signal 01 0
*l0000!dram_read signal 02 0
*l0000!dram_write signal 02 0
.%type R
.%type SI
.%scope global
.%var $$l0000!dr15 0 R
.%liverange 0 $$W15 3585:3585
.%liverange 0 $$R15 122:3583
.%var $$l0000!dr14 0 R
.%liverange 0 $$W14 3585:3585
.%liverange 0 $$R14 122:3583
.%var $$l0000!dr13 0 R
.%liverange 0 $$W13 3585:3585
.%liverange 0 $$R13 122:3583
.%var $$l0000!dr12 0 R
.%liverange 0 $$W12 3585:3585
.%liverange 0 $$R12 122:3583
.%var $$l0000!dr11 0 R
.%liverange 0 $$W11 3585:3585
.%liverange 0 $$R11 122:3583
.%var $$l0000!dr10 0 R
.%liverange 0 $$W10 3585:3585
.%liverange 0 $$R10 122:3583
.%var $$l0000!dr9 0 R
.%liverange 0 $$W9 3585:3585
.%liverange 0 $$R9 122:3583
.%var $$l0000!dr8 0 R
.%liverange 0 $$W8 3585:3585
.%liverange 0 $$R8 122:3583
.%var $$l0000!dr7 0 R
.%liverange 0 $$W7 3585:3585
.%liverange 0 $$R7 122:3583
.%var $$l0000!dr6 0 R
.%liverange 0 $$W6 3585:3585
.%liverange 0 $$R6 122:3583
.%var $$l0000!dr5 0 R
.%liverange 0 $$W5 3585:3585
.%liverange 0 $$R5 122:3583
.%var $$l0000!dr4 0 R
.%liverange 0 $$W4 3585:3585
.%liverange 0 $$R4 122:3583
.%var $$l0000!dr3 0 R
.%liverange 0 $$W3 3585:3585
.%liverange 0 $$R3 122:3583
.%var $$l0000!dr2 0 R
.%liverange 0 $$W2 3585:3585
.%liverange 0 $$R2 122:3583