media_lb_bd_on_sf_iface_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.1.55
+uca_date: Mar 24 2003 00:16:30
+current_date: Mon Apr 28 13:53:48 2003

.cpu_version 0x00000002 16 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:cont_init1# 3
:cont_init2# 23
:init_rbuf# 30
:init_value# 2
:receivepacket# 74
:rsw# 76
:set_refcnt_overwrite_bit# 84
*-- no_destination 0
*$l0000!transferreg00 sram_rel 00 0 both 2 0x35
*$l0000!transferreg01 sram_rel 01 0 both 1 0x35
;*l0000!rxthreadlist!!2 gpr_b_rel 05
;*l0000!rxthreadlist!!3 gpr_b_rel 05
*l0000!rxthreadlist gpr_a_rel 07
*l0000!bytecnt gpr_a_rel 00
*l0000!elem gpr_a_rel 01
*l0000!error gpr_b_rel 0A
*l0000!rx_channel_num gpr_b_rel 00
*l0000!cur_ctx gpr_a_rel 06
*@l0000!packet_count gpr_b_abs 01
;*l0000!rxconfigdata!!2 gpr_a_rel 02
*l0000!rxconfigdata gpr_b_rel 06
*l0000!rbuf gpr_a_rel 03
*l0000!ring_num gpr_b_rel 00
;*l0000!msfaddress!!2 gpr_b_rel 0B
;*l0000!msfaddress!!3 gpr_b_rel 0B
*l0000!msfaddress gpr_b_rel 0B
*l0000!threadfreelist_addr gpr_b_rel 02
*l0000!elementdone_addr gpr_a_rel 04
;*l0000!drampacketbase!!2 gpr_b_rel 03
*l0000!drampacketbase gpr_b_rel 03
*l0000!put_ring_num gpr_b_rel 04
*l0000!rx_count_ring_num gpr_b_rel 04
*l0001!temp gpr_b_rel 03
*l0001!cur_me gpr_b_rel 0F
*l0002!rxconfigdata0 gpr_b_rel 0C
*$l0002!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0003!temp_reg gpr_b_rel 05
*l0003!temp gpr_b_rel 06
*l0004!rxupcontrol gpr_b_rel 0D
*$l0004!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0005!rxconfigdata0 gpr_b_rel 0E
*$l0005!rxconfigdata0 sram_rel 00 0 both 1 0x0
*$l0006!scratch_base sram_rel 00 0 both 1 0x0
*$l0006!scratch_head sram_rel 01 0 both 1 0x0
*$l0006!scratch_tail sram_rel 02 0 both 1 0x0
*l0007!rbufoffset gpr_b_rel 07
;*l0007!refcnt!!2 gpr_a_rel 05
*l0007!refcnt gpr_b_rel 08
;*l0007!temp!!2 gpr_b_rel 09
;*l0007!temp!!3 gpr_b_rel 09
*l0007!temp gpr_b_rel 09
*$l0008!temp0 sram_rel 00 0 both 1 0x0
*$l0009!scratch_packet_count sram_rel 00 0 both 1 0x0
*l0009!scratch_sig signal 01 0
*l0006!scratch_sig3 signal 03 0
*l0006!scratch_sig3!!5 signal 03 0
*l0006!scratch_sig3!!4 signal 03 0
*l0006!scratch_sig3!!3 signal 03 0
*l0006!scratch_sig3!!2 signal 03 0
*l0006!scratch_sig2 signal 02 0
*l0006!scratch_sig2!!5 signal 02 0
*l0006!scratch_sig2!!4 signal 02 0
*l0006!scratch_sig2!!3 signal 02 0
*l0006!scratch_sig2!!2 signal 02 0
*l0006!scratch_sig1 signal 01 0
*l0006!scratch_sig1!!5 signal 01 0
*l0006!scratch_sig1!!4 signal 01 0
*l0006!scratch_sig1!!3 signal 01 0
*l0006!scratch_sig1!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig_thd signal 01 0
*l0000!sig_dram_xfer1 signal 02 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var $l0009!scratch_packet_count 0 R
.%liverange 0 $W0 95:96
.%liverange 0 ~$W0 74:91
.%liverange 0 $R0 97:97
.%var $l0008!temp0 0 R
.%liverange 0 $W0 92:94
.%liverange 0 $R0 97:97
.%var l0007!temp 0 R
.%liverange 0 B9 87:96
.%liverange 0 ~B9 74:86
.%var l0007!refcnt 0 R
.%liverange 0 B8 81:84
.%liverange 0 A5 85:96
.%liverange 0 ~A5 74:80
.%var l0007!rbufoffset 0 R
.%liverange 0 B7 86:96
.%liverange 0 ~B7 74:85
.%var $l0006!scratch_tail 0 R
.%liverange 0 $W2 46:73
.%liverange 0 ~$W2 74:96
.%liverange 0 $R2 97:97
.%var $l0006!scratch_head 0 R
.%liverange 0 $W1 45:73
.%liverange 0 ~$W1 74:96
.%liverange 0 $R1 97:97
.%var $l0006!scratch_base 0 R
.%liverange 0 $W0 47:73
.%liverange 0 ~$W0 74:91
.%liverange 0 $R0 97:97
.%var $l0005!rxconfigdata0 0 R
.%liverange 0 $W0 42:46
.%liverange 0 $R0 97:97
.%var l0005!rxconfigdata0 0 R
.%liverange 0 B14 40:73
.%liverange 0 ~B14 74:96
.%var $l0004!rxconfigdata0 0 R
.%liverange 0 $W0 37:41
.%liverange 0 $R0 97:97
.%var l0004!rxupcontrol 0 R
.%liverange 0 B13 36:73
.%liverange 0 ~B13 74:96
.%var l0003!temp 0 R
.%liverange 0 B6 31:73
.%liverange 0 ~B6 30:30 74:96
.%var l0003!temp_reg 0 R
.%liverange 0 B5 30:73
.%liverange 0 ~B5 74:96
.%var $l0002!rxconfigdata0 0 R
.%liverange 0 $W0 27:36
.%liverange 0 $R0 97:97
.%var l0002!rxconfigdata0 0 R
.%liverange 0 B12 25:73
.%liverange 0 ~B12 74:96
.%var l0001!cur_me 0 R
.%liverange 0 B15 6:96
.%var l0001!temp 0 R
.%liverange 0 B3 5:13
.%var l0000!rx_count_ring_num 0 R
.%liverange 0 B4 18:96
.%var l0000!put_ring_num 0 R
.%liverange 0 B4 17:17
.%var l0000!drampacketbase 0 R
.%liverange 0 B3 14:96
.%var l0000!elementdone_addr 0 R
.%liverange 0 A4 19:96
.%var l0000!threadfreelist_addr 0 R
.%liverange 0 B2 3:96
.%var l0000!msfaddress 0 R
.%liverange 0 B11 28:73
.%liverange 0 ~B11 74:96
.%var l0000!ring_num 0 R
.%liverange 0 B0 8:73
.%liverange 0 ~B0 74:79
.%var l0000!rbuf 0 R
.%liverange 0 A3 20:96
.%var l0000!rxconfigdata 0 R
.%liverange 0 B6 12:12
.%liverange 0 A2 13:96
.%var @l0000!packet_count 0 R
.%liverange 0 @B1 0:96
.%var l0000!cur_ctx 0 R
.%liverange 0 A6 7:96
.%var l0000!rx_channel_num 0 R
.%liverange 0 B0 80:96
.%liverange 0 ~B0 74:79
.%var l0000!error 0 R
.%liverange 0 B10 79:96
.%liverange 0 ~B10 74:78
.%var l0000!elem 0 R
.%liverange 0 A1 77:96
.%liverange 0 ~A1 74:76
.%var l0000!bytecnt 0 R
.%liverange 0 A0 78:96
.%liverange 0 ~A0 74:77
.%var l0000!rxthreadlist 0 R
.%liverange 0 A7 9:9
.%liverange 0 B5 10:29
.%liverange 0 ~B5 74:96
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 97:97
.%liverange 0 $R1 97:97
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:26
.%liverange 0 ~$W0 74:91
.%liverange 0 $R0 0:96
.%var l0009!scratch_sig 1 R
.%liverange 0 G1 96:96
.%var l0006!scratch_sig3 1 R
.%liverange 0 G3 50:51 55:56 60:61 65:66 70:71
.%var l0006!scratch_sig2 1 R
.%liverange 0 G2 49:51 54:56 59:61 64:66 69:71
.%var l0006!scratch_sig1 1 R
.%liverange 0 G1 48:51 53:56 58:61 63:66 68:71
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:0 2:22
.%var l0000!rx_sig_thd 1 R