msf_unicast_tx.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* msf_unicast_tx.uc
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXP2400
 *  subsystem: DIAG
 *  author: dalsraja, March, 2002
 *  revisions:
 * 
 * 
 * --------------------------------------------------------------------------
 */

#include "common_uc.h"

#define TX_ELEMENTSIZE			MSF_ELEMENTSIZE_128
#define TX_ENABLE_MASK			0x1
#define TX_MODE					MSF_CSIX
#define TX_WIDTH				MSF_WIDTH_1x32
#define TX_SINGLE_PHY			MSF_SINGLE_PHY

#define CSIX_PAYLOAD_LENGTH		64
#define CSIX_TYPE_UNICAST		1			// CSIX Type = Unicast

#define EXT_HDR					0x11223344

#define DRAM_BASE_SRC			0x1000000

.reg temp1
.reg MsfAddress
.reg TxConfigData0 $TxConfigData0
.reg $TxControlWord0 $TxControlWord1
.reg tbuf_element
.reg dram_addr tbuf
.sig dram_sig msf_sig

.xfer_order $TxControlWord0 $TxControlWord1

br=ctx[0, init#]
ctx_arb[kill]

init#:

	immed[tbuf, RBUF_TBUF]
	immed[tbuf_element, 0]

	immed[dram_addr, (DRAM_BASE_SRC & MASK_16BIT)]
	immed_w1[dram_addr, (DRAM_BASE_SRC >> 16)]


//****************************************************
// Configure TX Control
//****************************************************
	immed[MsfAddress, MSF_TX_CONTROL]
	immed[TxConfigData0, (TX_ELEMENTSIZE << 2)]	// put control and data into diff freelist
	immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]

	alu[$TxConfigData0, TxConfigData0, OR, TX_ENABLE_MASK, <<28]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


#ifdef WORKBENCH_SIM
start#:
.begin
	.reg temp_addr $scratch_data
	.sig scratch_sig

	immed[temp_addr, 0x200]
wait_here#:
	scratch[read, $scratch_data, temp_addr, 0, 1], ctx_swap[scratch_sig]
	alu[--, $scratch_data, -, 0]
	bne[wait_here#]
.end
#endif


//****************************************************
// Move data to TBUF from DRAM - Use a 64 byte packet
//****************************************************
	alu[tbuf, --, B, tbuf, <<5]
	alu[--, tbuf, OR, 1, <<4]		// set the overwrite bit for the TBUF addr
	dram[tbuf_wr, --, dram_addr, 0, 8], indirect_ref, sig_done[dram_sig]
	ctx_arb[dram_sig]

#ifdef MSF_WORKAROUND
	alu[--, tbuf, OR, 1, <<4]		// set the overwrite bit for the TBUF addr
	dram[tbuf_wr, --, dram_addr, 0, 2], indirect_ref, sig_done[dram_sig]
	ctx_arb[dram_sig]	
#endif	


//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
	immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]

	immed[temp1, CSIX_TYPE_UNICAST]
	alu[$TxControlWord0, temp1, OR, CSIX_PAYLOAD_LENGTH, <<24]

	immed[temp1, (EXT_HDR & MASK_16BIT)]
	immed_w1[temp1, ((EXT_HDR >> 16) & MASK_16BIT)]
	alu[$TxControlWord1, --, B, temp1]

	// Tx Control longword 0 = 0x40000001 (64 byte payload, CSIX type 1)
	// Tx Control longword 1 = 0x11223344 (extension header)
	msf[write, $TxControlWord0, MsfAddress, 0, 2], ctx_swap[msf_sig]

/*
.begin
	.reg $$d0 $$d1 $s0 $s1 s_addr d_ctr
	.xfer_order $s0 $s1
	.xfer_order $$d0 $$d1
	.sig scratch_sig

	immed[s_addr, 0x500]
	immed[d_ctr, 0]

check_dram_data#:
	dram[read, $$d0, dram_addr, d_ctr, 1], sig_done[dram_sig]
	ctx_arb[dram_sig]
	alu[$s0, --, B, $$d0]
	alu[$s1, --, B, $$d1]
	scratch[write, $s0, s_addr, d_ctr, 2], ctx_swap[scratch_sig]

	alu[d_ctr, d_ctr, +, 8]
	.if (d_ctr < 64)
		br[check_dram_data#]
	.endif
.end
*/


//*****************************************************************
//  Write to MAILBOX0 register to signal completion to XScale code
//*****************************************************************
#ifndef WORKBENCH_SIM
.begin
	.reg pci_base pci_offset temp
	.reg $pci_rw
	.sig pci_sig

	immed[pci_base, (PCI_LOCAL_CSR_BASE & MASK_16BIT)]
	immed_w1[pci_base, ((PCI_LOCAL_CSR_BASE >> 16) & MASK_16BIT)]
	immed[pci_offset, MAILBOX0_OFFSET]
	immed[temp, 0]
	immed_w1[temp, PACKET_SENT]
	alu[$pci_rw, --, B, temp]
	pci[write, $pci_rw, pci_base, pci_offset, 1], ctx_swap[pci_sig]
.end
#endif

end#:
ctx_arb[kill]