msf_unicast_rx.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* msf_unicast_rx.uc
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXP2400
 *  subsystem: DIAG
 *  author: dalsraja, March, 2002
 *  revisions:
 * 
 * 
 * --------------------------------------------------------------------------
 */

#include "common_uc.h"

#define RX_SINGLE_PHY			MSF_SINGLE_PHY
#define RX_WIDTH				MSF_WIDTH_1x32
#define RX_ENABLE_MASK			0x1
#define RX_MODE					MSF_CSIX
#define RX_ELEMENT_SIZE			MSF_ELEMENTSIZE_128
#define RBUF_ELEM_COUNT			(1 << (7 - RX_ELEMENT_SIZE))				// Tot. elements
#define RBUF_DATA_ELEM_COUNT	(RBUF_ELEM_COUNT >> 2) * 3)	// (Tot. elements / 4) * 3
#define RX_ELEMENT_SIZE_BYTE	(1 << (6 + RX_ELEMENT_SIZE))

#define RX_TRANSFER_THREAD		&$TransferReg00
#define RX_SIGNAL_THREAD		&sig_thd

#define DRAM_BASE				0x1000000


.reg $TransferReg00 $TransferReg01
.reg $temp0 $temp1
.reg RxThreadList 
.reg class bytecnt elem
.reg RxConfigData0 $RxConfigData $RxConfigData0
.reg rbuf Rbufoffset 
.reg MsfAddress MsfAddress0 MsfAddress1
.reg dramPacketBase 

.sig msf_sig scratch1 sig_thd sig_dram_xfer1
.xfer_order $TransferReg00 $TransferReg01

.set_sig sig_thd
.set $TransferReg00 $TransferReg01


	br=ctx[0, Init_Value#]
	ctx_arb[kill]


Init_Value#:

#ifdef WORKBENCH_SIM
#define INTER_THD_SIG_NUM	15
	.begin

	.sig inter_thd_sig
	.addr inter_thd_sig INTER_THD_SIG_NUM
	.set_sig inter_thd_sig

		ctx_arb[inter_thd_sig]
	.end
#endif

	immed[dramPacketBase, (DRAM_BASE & MASK_16BIT)]
	immed_w1[dramPacketBase, (DRAM_BASE >> 16)]


//****************************************************
// Configure RX/TX Control
//****************************************************

	immed[RxConfigData0, ((0<<9)|(RX_ELEMENT_SIZE << 2))] // put control and data into diff freelist
	immed_w1[RxConfigData0, ((RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
	alu[$RxConfigData0, --, B, RxConfigData0]
	immed[MsfAddress, MSF_RX_CONTROL]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]

	alu[$temp1, --, B, MSF_CSIX_RBUF_DATA, <<BIT_SHF_UNICAST]
	immed[MsfAddress, CSIX_TYPE_MAP]
	msf[write, $temp1, MsfAddress, 0, 1], ctx_swap[msf_sig]


//******************************************************
// Initialize RBUF Freelist to add elements to the list
//******************************************************
.begin
	.reg temp_reg temp

	immed[temp_reg, 0]

init_RBUF#:
	alu[temp, --, B, temp_reg, <<16]
	msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
	alu[temp_reg, temp_reg, +, 1]
	alu[--, RBUF_ELEM_COUNT, -, temp_reg]
	bne[init_RBUF#]
.end


	immed[RxConfigData0, ((0<<9)|(RX_ELEMENT_SIZE << 2))] // put control and data into diff freelist
	immed_w1[RxConfigData0, ((RX_ENABLE_MASK << 12) | (RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
	alu[$RxConfigData0, --, B, RxConfigData0]
	immed[MsfAddress, MSF_RX_CONTROL]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


context_enable_csr_config#:
//**********************************************************
// Program CSR Context Enables, used by the context arbiter
//**********************************************************

// Initialize CTX_Enables CSR (Put into 8 CTX mode) 
// Bit 31: In-Use contexts: 0 = 8 ctx mode, 1 = 4 ctx mode
// Bit 20: Next Neighbour registers are written from this ME
// Bit  17, 1=LM_ADDR_1 is GLOBAL, 0=LM_ADDR_1 is context_relative
// Bit  16, 1=LM_ADDR_0 is GLOBAL, 0=LM_ADDR_0 is context_relative
// Bits [15:8] CTX enables for contexts 7:0

#define In_Use_Contexts				0
#define Control_Store_Parity_Error	0
#define Control_Store_Parity_Enable	0
#define Breakpoint					0
#define NN_Mode						1
#define NN_Ring_Empty				0
#define LM_ADDR_1_Global			0
#define	LM_ADDR_0_Global			0

#define Enable						0xff


//*******************************************
// Configure Ctx_Enables
//*******************************************
.begin
	.reg CtxEnableData

	immed[CtxEnableData, (Enable << 8)]
	immed_w1[CtxEnableData, ((In_Use_Contexts << 15)|(Control_Store_Parity_Error << 13)|(Control_Store_Parity_Enable << 12)|(Breakpoint << 11)|(NN_Mode << 4)|(NN_Ring_Empty << 2)|(LM_ADDR_1_Global << 1)|(LM_ADDR_0_Global << 0))]
	local_csr_wr[CTX_Enables, CtxEnableData]
.end


InitStart#:
.begin
	.reg cur_me, cur_ctx tmp_val temp
	local_csr_rd[ACTIVE_CTX_STS]
	immed[temp, 0]
	alu[tmp_val, 0x4, AND, temp, >>5]
	alu[cur_me, 0x3, AND, temp, >>3]
	alu[cur_me, cur_me, OR, tmp_val]	// Extract the current ME number
	alu[cur_ctx, 0x7, AND, temp]		// Extract the current context number
	immed[RxThreadList, (RX_SIGNAL_THREAD << 12)]
	alu[RxThreadList, RxThreadList, OR, cur_me, <<7]
	alu[RxThreadList, RxThreadList, OR, cur_ctx, <<4]
.end


Init_Common#:
	immed[rbuf, RBUF_TBUF ]
	immed[MsfAddress0, RX_THREAD_FREELIST_0]
	immed[MsfAddress1, RBUF_ELEMENT_DONE]
	alu[RxConfigData0, RxThreadList,  OR , RX_TRANSFER_THREAD]
	alu[RxConfigData0, --,  B, RxConfigData0, <<16]		// For msf[fast_wr...]


ReceivePacket#:
	msf[fast_wr, --, MsfAddress0, RxConfigData0] // add thread to freelist
	ctx_arb[sig_thd]


// RSW should be in xfer register
//***************************************
// Extract RSW
//****************************************
RSW#:
	alu_shf[elem, 0x7f, AND, $TransferReg00, >>24]  // get element number
	alu_shf[bytecnt, 0xff, AND, $TransferReg00, >>16]  // get pkt len


//*********************************
// Transfer from ME to DRAM
//*********************************
.begin
	.reg pkt_buff_addr rel temp sr0
#ifdef MSF_WORKAROUND
	.reg tmp1
	immed[tmp1, 48]
	alu_shf[RBufOffset, --, B, tmp1, <<7]		// 128B
	alu[temp, RBuf, +, RBufOffset]
	alu[--, 0x10, or, temp, <<5]
	dram[rbuf_rd, --, dramPacketBase, 0, 8], indirect_ref, sig_done[sig_dram_xfer1]	
	ctx_arb[sig_dram_xfer1]
#endif
	alu_shf[RBufOffset, --, B, elem, <<7]		// 128B
	alu[temp, RBuf, +, RBufOffset]
	alu[--, 0x10, or, temp,<<5]
	dram[rbuf_rd, --, dramPacketBase, 0, 8], indirect_ref, sig_done[sig_dram_xfer1]	
	ctx_arb[sig_dram_xfer1]
.end

//**************************************************************
//  Free up Element by writing to RBUF_Element_Done{Channel}
//**************************************************************
	alu[$temp0, --, B, elem]
	msf[write, $temp0, MsfAddress1,0, 1], ctx_swap[msf_sig]


//*****************************************************************
//  Write to MAILBOX0 register to signal completion to XScale code
//*****************************************************************
#ifndef WORKBENCH_SIM
.begin
	.reg $pci_rw pci_base pci_offset temp
	.sig pci_sig
	immed[temp, 0]
	immed_w1[temp, TEST_COMPLETE]
	alu[$pci_rw, --, B, temp]
	immed[pci_base, (PCI_LOCAL_CSR_BASE & MASK_16BIT)]
	immed_w1[pci_base, (PCI_LOCAL_CSR_BASE >> 16)]
	immed[pci_offset, MAILBOX0_OFFSET]
	pci[write, $pci_rw, pci_base, pci_offset, 1], ctx_swap[pci_sig]	// To signal XScale
	alu[$pci_rw, --, B, $TransferReg00]
	immed[pci_offset, MAILBOX1_OFFSET]
.end
#endif

end#:
ctx_arb[kill]