sys_loopback_bd_eg_tx.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* sys_loopback_eg_tx.uc
 *
 * This file transmits POS packets from DRAM. If the number of transmitted
 * packets is not equals to the number that have to be transmitted, it polls
 * on scratch for a signal from the receive ME. When it receives the signal
 * from the receive ME, it extracts the DRAM address where the packet to be
 * transmitted is stored and transmits it. If the number of transmitted
 * packets is equal to the number that have to be transmitted, it signals the
 * XScale that it has completed all the transmitting.
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXDP2400
 *  subsystem: DIAG
 *  author: dalsraja, April, 2002
 *  revisions:  dalsraja, May 8, 2002
 * 
 * 
 * --------------------------------------------------------------------------
 */

#include "common_uc.h"

#define TX_ELEMENT_SIZE				MSF_ELEMENTSIZE_128
#define TX_ENABLE_MASK				0x1
#define TX_MODE						MSF_POS_UTOPIA
#define TX_WIDTH					MSF_WIDTH_1x32
#define TX_SINGLE_PHY				MSF_SINGLE_PHY

#define POS_PAYLOAD_LENGTH			64
#define TX_CONTROL_EOP				(1 << 8)
#define TX_CONTROL_SOP				(1 << 9)
#define SOPEOP_SHF					8

#define TBUF_ELEM_COUNT				(1 << (7 - TX_ELEMENT_SIZE))
#define TBUF_ADDR_SHF				(6 + TX_ELEMENT_SIZE)
#define TX_ELEMENTSIZE_BYTE			(1 << TBUF_ADDR_SHF)

#define ME_NUMBER_RX				0
#define ME_NUMBER_TX				1
#define RX_THD_NUM					0
#define INTERTHD_SIG_NUM			15
#define MESSAGE_ADDR				0x200
#define ORIG_PKT_DRAM_ADDR			0x1000000		// Original packet stored in 16 Meg
#define ORIG_PACKET_SIZE			64

.reg scratch_addr total_byte_count byte_count packet_count ring_num //scr_add
.reg packet_status packet_size sopeop
.reg $temp
.reg MsfAddress MsfAddress0 MsfAddress1
.reg TxConfigData0
.reg $TxConfigData0
.reg $TxControlWord0 $TxControlWord1
.reg tbuf_element
.reg dram_base dram_addr tbuf
.reg $scratch_data0 $scratch_data1
.sig dram_sig msf_sig interthd_sig cap_sig scratch_sig

.addr interthd_sig INTERTHD_SIG_NUM

.xfer_order $TxControlWord0 $TxControlWord1
.xfer_order $scratch_data0 $scratch_data1

.set_sig interthd_sig

ctx_arb[interthd_sig]

br=ctx[0, init#]
ctx_arb[kill]

init#:
	immed[tbuf_element, 0]
	immed[scratch_addr, MESSAGE_ADDR]
//	immed[scr_add, 0x400]

	immed[dram_base, (ORIG_PKT_DRAM_ADDR & MASK_16BIT)]
	immed_w1[dram_base, ((ORIG_PKT_DRAM_ADDR >> 16) & MASK_16BIT)]
	immed[byte_count, ORIG_PACKET_SIZE]	
	immed[packet_count, 0]
	immed[packet_status, 0]
	immed[ring_num, RING_0]


//****************************************************
// Configure TX Control
//****************************************************
	immed[tbuf, RBUF_TBUF]
	immed[MsfAddress, MSF_TX_CONTROL]
	immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)]	// put control and data into diff freelist
	immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


//******************************************************
// Configure TX UP Control CSRs 
//******************************************************
	immed[MsfAddress, TX_UP_CONTROL_0]
	immed[TxConfigData0, (UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


//****************************************************
// Configure TX Control
//****************************************************
	immed[MsfAddress, MSF_TX_CONTROL]
	immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)]	// put control and data into diff freelist
	immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 12) | (TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]

.reg temp_scratch_addr
	immed[temp_scratch_addr, 0x1000]

get_packet_data#:
	scratch[get, $scratch_data0, ring_num, 0, 1], ctx_swap[scratch_sig]
	alu[--, $scratch_data0, -, 0]
	beq[get_packet_data#]		// branch to label if there is no new assignment

.local temp_mask
	immed[temp_mask, 0xFFFF]
	alu[packet_size, temp_mask, AND, $scratch_data0]
	immed[temp_mask, 0xFF00]
	alu[dram_addr, temp_mask, AND, $scratch_data0, >>8]
	alu[dram_addr, dram_base, +, dram_addr]
.endlocal

.begin
	.reg $reg0 $reg1 $reg2
	.xfer_order $reg0 $reg1 $reg2

	alu[$reg0, --, B, $scratch_data0]
	alu[$reg1, --, B, packet_size]
	alu[$reg2, --, B, dram_addr]
	scratch[write, $reg0, temp_scratch_addr, 0, 3], ctx_swap[scratch_sig]
	alu[temp_scratch_addr, temp_scratch_addr, +, 16]
.end

transmit#:

//****************************************************
// Move data to TBUF from DRAM
//****************************************************
.begin
	.reg cur_tbuf_addr refcnt

	.if (packet_status == 0)
		.if (packet_size <= TX_ELEMENTSIZE_BYTE)
			alu[byte_count, --, B, packet_size]
			immed[sopeop, SOP_EOP]
		.else
			immed[byte_count, TX_ELEMENTSIZE_BYTE]
			immed[sopeop, SOP_NOEOP]
		.endif
	.else
		alu[byte_count, packet_size, -, packet_status]
		.if (byte_count > TX_ELEMENTSIZE_BYTE)
			immed[byte_count, TX_ELEMENTSIZE_BYTE]
			immed[sopeop, MOP]
		.else
			immed[sopeop, NOSOP_EOP]
		.endif
	.endif

	alu[cur_tbuf_addr, tbuf, OR, tbuf_element, <<TBUF_ADDR_SHF]
	alu[cur_tbuf_addr, --, B, cur_tbuf_addr, <<5]
	alu[cur_tbuf_addr, cur_tbuf_addr, OR, 1, <<4]		// set the overwrite bit for the TBUF addr
	alu[refcnt, --, B, byte_count, >>3]
	alu[--, byte_count, AND, 0x7]
	beq[cont1#]
	alu[refcnt, refcnt, +, 1]			// Calculate the refcnt for indirect ref

cont1#:
	.if (refcnt > 15)		// This is assuming that the RBUF Element are always 128 bytes
		immed[refcnt, 15]
	.endif
	alu[refcnt, --, B, refcnt, <<21]	// Shift to appropriate bit
	alu[refcnt, refcnt, OR, 1, <<25]	// Set the overwrite bit for refcnt

	alu[--, cur_tbuf_addr, OR, refcnt]	// indirect ref
	dram[tbuf_wr, --, dram_addr, packet_status, 8], indirect_ref, sig_done[dram_sig]
	ctx_arb[dram_sig]	

#ifdef MSF_WORKAROUND
	alu[--, --, B, cur_tbuf_addr]	// indirect ref
	dram[tbuf_wr, --, dram_addr, packet_status, 2], indirect_ref, sig_done[dram_sig]
	ctx_arb[dram_sig]
#endif	
.end


//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
.begin
	.reg temp

	immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]
	alu[MsfAddress, MsfAddress, OR, tbuf_element, <<3] //TBUF_CTRL_ADDR_SHF
	alu[temp, --, B, sopeop, <<SOPEOP_SHF]
	alu[$TxControlWord0, temp, OR, byte_count, <<24]

	immed[$TxControlWord1, 0]

	msf[write, $TxControlWord0, MsfAddress, 0, 2], ctx_swap[msf_sig]
.end

	alu[tbuf_element, tbuf_element, +, 1]
	alu[tbuf_element, tbuf_element, AND, (TBUF_ELEM_COUNT - 1)]
	alu[packet_status, packet_status, +, byte_count]

//	immed[$scratch_data0, 0]
//	scratch[write, $scratch_data0, scratch_addr, 0, 1], ctx_swap[scratch_sig]

	.if (packet_size != packet_status)
		br[transmit#]
	.endif

	immed[packet_status, 0]
	br[get_packet_data#]

/*
.begin
	.reg scratch_add $s_xfer tmp_val

//	alu[tmp_val, dram_addr, +, packet_status]
	alu[$s_xfer, --, B, $scratch_data0]
	scratch[write, $s_xfer, scr_add, 0, 1], ctx_swap[scratch_sig]
	alu[scr_add, scr_add, +, 4]
.end
*/

/*
.begin
	.reg scratch_add $s_xfer

	immed[scratch_add, 0x40C]
	alu[$s_xfer, --, B, packet_count]
	scratch[write, $s_xfer, scratch_add, 0, 1], ctx_swap[scratch_sig]
.end
*/