📄 sys_loopback_bd_in_rx.uc
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/* sys_loopback_in_rx.uc
*
* This file receives POS packets and stores them in DRAM. Once it receives
* a packet, it writes the DRAM address to scratch and sends a signal to
* the transmit ME through an interthread signal. It than checks the number
* of received packets. If the expected number of packets is reached, it
* signals the XScale through the mailbox register
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, April, 2002
* revisions: dalsraja, May 8, 2002
*
*
* --------------------------------------------------------------------------
*/
#include "common_uc.h"
#define RX_SINGLE_PHY MSF_SINGLE_PHY
#define RX_WIDTH MSF_WIDTH_1x32
#define RX_ENABLE_MASK 0x1
#define RX_MODE MSF_POS_UTOPIA
#define RX_ELEMENTSIZE MSF_ELEMENTSIZE_128
#define RBUF_ELEM_COUNT (1 << (7 - RX_ELEMENTSIZE))
#define RBUF_ADDR_SHF (6 + RX_ELEMENTSIZE)
#define RX_ELEMENTSIZE_BYTE (1 << RBUF_ADDR_SHF)
#define ME_NUMBER_RX 0
#define ME_NUMBER_TX 1
#define TX_THD_NUM 0
#define INTERTHD_SIG_NUM 15
#define RX_TRANSFER_THREAD &$TransferReg00
#define RX_SIGNAL_THREAD &rx_sig_thd
#define SRAM_DESC_BASE 0x200000 // 2 Meg onwards
#define DRAM_PCKT_BASE 0x1000000 // 16 Meg onwards
#define MESSAGE_ADDR 0x200 // For messaging between MEs
.reg ring_num packet_size pkt_buff_addr bdptr
.reg $TransferReg00 $TransferReg01 $scratch_data
.reg temp t0 $temp packet_count
.reg RxThreadList sopeop sopbit eopbit bytecnt elem
.reg $RxConfigData $RxConfigData0 RxConfigData0
.reg rbuf scratch_addr
.reg MsfAddress
.reg sramDescBase dramPacketBase
.reg mask_qa error
.reg RxUPControl0
.reg $sr0 $sr1 $sr2 $sr3
.sig msf_sig scratch_sig dram_sig sram_sig
.sig rx_sig_thd interthd_sig
.xfer_order $TransferReg00 $TransferReg01
.xfer_order $sr0 $sr1 $sr2 $sr3
.addr interthd_sig INTERTHD_SIG_NUM
.set $TransferReg00
.set_sig interthd_sig
ctx_arb[interthd_sig]
br=ctx[0, Init_Value#]
ctx_arb[kill]
Init_Value#:
immed[scratch_addr, MESSAGE_ADDR]
immed[packet_count, 0]
immed[packet_size, 0]
immed[pkt_buff_addr, 0]
immed[bdptr, 0]
alu[ring_num, --, B, RING_0, <<2] // ring number in a register
.local channel_number
alu[channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
alu[t0, channel_number, OR, Q_NUMBER, <<SRAM_Q_ARRAY_NUMBER_FIELD]
.endlocal
immed[dramPacketBase, (DRAM_PCKT_BASE & MASK_16BIT)]
immed_w1[dramPacketBase, ((DRAM_PCKT_BASE >> 16) & MASK_16BIT)]
immed[sramDescBase, (SRAM_DESC_BASE & MASK_16BIT)]
immed_w1[sramDescBase, ((SRAM_DESC_BASE >> 16) & MASK_16BIT)]
//****************************************
// Configure for ctx0
//***************************************
immed[RBuf, RBUF_TBUF ]
immed[RxThreadList, ((RX_SIGNAL_THREAD << 12) | (ME_NUMBER_RX << 7) | (0 << 4))]
alu[$RxConfigData, RxThreadList, OR , RX_TRANSFER_THREAD]
//****************************************************
// Configure RX/TX Control
//****************************************************
immed[MsfAddress, MSF_RX_CONTROL]
immed[RxConfigData0, ((0 << 9) | (RX_ELEMENTSIZE << 2))]
immed_w1[RxConfigData0, ((RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
alu[$RxConfigData0, --, B, RxConfigData0]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
//******************************************************
// Initialize RBUF Freelist to add elements to the list
//******************************************************
.begin
.reg temp_reg temp
immed[temp_reg, 0]
init_RBUF#:
alu[temp, --, B, temp_reg, <<16]
msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
alu[temp_reg, temp_reg, +, 1]
alu[--, RBUF_ELEM_COUNT, -, temp_reg]
bne[init_RBUF#]
.end
//******************************************************
// Configure RX UP Control CSRs
//******************************************************
immed[MsfAddress, RX_UP_CONTROL_0]
immed[RxUPControl0, (UP_CTRL_PP_MODE | UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
alu[$RxConfigData0, --, B, RxUPControl0]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
//****************************************************
// Configure RX/TX Control
//****************************************************
immed[MsfAddress, MSF_RX_CONTROL]
immed[RxConfigData0, ((0 << 9) | (RX_ELEMENTSIZE << 2))]
immed_w1[RxConfigData0, ((RX_ENABLE_MASK << 12) | (RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
alu[$RxConfigData0, --, B, RxConfigData0]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.begin
.reg sw0 sw1 sw2 sw3 cellcount freelist sr0
.reg $s0 $s1 $s2
.reg tmp spin
.sig qa_init addr
.xfer_order $s0 $s1 $s2
alu[tmp, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
alu[tmp, tmp, OR, sramDescBase]
immed[$s0, 0]
immed[$s1, 0]
immed[$s2, 0]
sram[write, $s0, tmp, 0, 3], ctx_swap[qa_init]
alu[tmp, --, B, sramDescBase]
alu[tmp, --, B, tmp, >>2]
sram[rd_qdesc_head, $sr0, t0, tmp, 2], ctx_swap[qa_init]
sram[rd_qdesc_other, --, t0, tmp]
immed[freelist, 20]
// immed[freelist, (FREELIST_SIZE & MASK_16BIT)]
// immed_w1[freelist, ((FREELIST_SIZE >> 16) & MASK_16BIT)]
immed[cellcount, 0x1c, <<16] //set cell count to 1, set OV EOP, and SOP
addfreelist#:
alu[--, cellcount, OR, 0]
sram[enqueue, --, t0, tmp], indirect_ref
alu[tmp, tmp, +, 1]
alu[freelist, freelist, -, 1]
bne[addfreelist#]
.end
context_enable_csr_config#:
//**********************************************************
// Program CSR Context Enables, used by the context arbiter
//**********************************************************
// Initialize CTX_Enables CSR (Put into 8 CTX mode)
// Bit 31: In-Use contexts: 0 = 8 ctx mode, 1 = 4 ctx mode
// Bit 20: Next Neighbour registers are written from this ME
// Bit 17, 1=LM_ADDR_1 is GLOBAL, 0=LM_ADDR_1 is context_relative
// Bit 16, 1=LM_ADDR_0 is GLOBAL, 0=LM_ADDR_0 is context_relative
// Bits [15:8] CTX enables for contexts 7:0
#define In_Use_Contexts 0
#define Control_Store_Parity_Error 0
#define Control_Store_Parity_Enable 0
#define Breakpoint 0
#define NN_Mode 1
#define NN_Ring_Empty 0
#define LM_ADDR_1_Global 0
#define LM_ADDR_0_Global 0
#define Enable 0xff
//*******************************************
// Configure Ctx_Enables
//*******************************************
.begin
.reg CtxEnableData
immed[CtxEnableData, (Enable << 8)]
immed_w1[CtxEnableData, ((In_Use_Contexts << 15)|(Control_Store_Parity_Error << 13)|(Control_Store_Parity_Enable << 12)|(Breakpoint << 11)|(NN_Mode << 4)|(NN_Ring_Empty << 2)|(LM_ADDR_1_Global << 1)|(LM_ADDR_0_Global << 0))]
local_csr_wr[CTX_Enables, CtxEnableData]
.end
//*****************************************************************
// Write to MAILBOX0 register to signal completion to XScale code
//*****************************************************************
#ifndef WORKBENCH_SIM
.begin
.reg pci_base pci_offset temp
.reg $pci_rw
.sig pci_sig
immed[pci_base, (PCI_LOCAL_CSR_BASE & 0xFFFF)]
immed_w1[pci_base, (PCI_LOCAL_CSR_BASE >> 16)]
immed[pci_offset, MAILBOX0_OFFSET]
immed[temp, PACKET_RECEIVED]
alu[$pci_rw, --, B, temp]
pci[write, $pci_rw, pci_base, pci_offset, 1], ctx_swap[pci_sig]
.end
#endif
immed[MsfAddress, RX_THREAD_FREELIST_0]
//********************************************************
// Start of Receive
//********************************************************
ReceivePacket#:
.set_sig rx_sig_thd
msf[write, $RxConfigData, MsfAddress, 0, 1], sig_done[msf_sig]
ctx_arb[msf_sig, rx_sig_thd]
// RSW should be in xfer register
// Transfer RBUF data to sram_in transfer registers
//***************************************
// Extract RSW
//****************************************
RSW#:
alu_shf[elem, --, B, $TransferReg00, >>24] // Get element number
alu[sopbit, 0x1, AND, $TransferReg00, >>15] // Check SOP
alu[eopbit, 0x1, AND, $TransferReg00, >>14] // Check EOP
alu[bytecnt, 0xFF, AND, $TransferReg00, >>16] // Extract byte count
alu[error, 0x1, AND, $TransferReg00, >>13] // Extract error
bne[free_element#] // If error, branch
.begin
.reg cur_rbuf_addr refcnt $scratch_data0 $scratch_data1
.reg rel freebuffer
.xfer_order $scratch_data0 $scratch_data1
.sig sig_free_buf
.if (packet_size == 0)
sram[dequeue, $sr0, t0, 0], ctx_swap[sig_free_buf]
alu[freebuffer, --, B, $sr0, <<2] // Shift 2 as address obtained is longword address
alu[bdptr, freebuffer, -, sramDescBase]
alu[rel, --, B, bdptr, <<6]
alu[pkt_buff_addr, dramPacketBase, +, rel]
.endif
//*********************************
// Transfer from ME to DRAM
//*********************************
alu[cur_rbuf_addr, rbuf, OR, elem, <<RBUF_ADDR_SHF]
alu[cur_rbuf_addr, --, B, cur_rbuf_addr, <<5]
alu[cur_rbuf_addr, cur_rbuf_addr, OR, 1, <<4] // set the overwrite bit for the RBUF addr
alu[refcnt, --, B, bytecnt, >>3]
alu[--, bytecnt, AND, 0x7]
beq[cont1#]
alu[refcnt, refcnt, +, 1] // Calculate the refcnt for indirect ref
cont1#:
.if (refcnt > 15) // This is assuming that the RBUF Element are always 128 bytes
immed[refcnt, 15]
.endif
#ifdef MSF_WORKAROUND
.local tmp_elem tmp_rbuf_addr $tmp_xfer0 $tmp_xfer1
.xfer_order $tmp_xfer0 $tmp_xfer1
alu[tmp_elem, elem, +, 1]
alu[tmp_elem, tmp_elem, AND, (RBUF_ELEM_COUNT - 1)]
alu[tmp_rbuf_addr, rbuf, OR, tmp_elem, <<RBUF_ADDR_SHF]
msf[read, $tmp_xfer0, tmp_rbuf_addr, packet_size, 1], ctx_swap[msf_sig]
.endlocal
#endif
alu[refcnt, --, B, refcnt, <<21] // Shift to appropriate bit
alu[refcnt, refcnt, OR, 1, <<25] // Set the overwrite bit for refcnt
alu[--, cur_rbuf_addr, OR, refcnt] // indirect ref
dram[rbuf_rd, --, pkt_buff_addr, packet_size, 8], indirect_ref, sig_done[dram_sig]
// alu[$scratch_data0, --, B, dramPacketBase]
// alu[$scratch_data1, --, B, bytecnt]
// scratch[write, $scratch_data0, scratch_addr, 0, 2], sig_done[scratch_sig]
ctx_arb[dram_sig]
.end
free_element#:
//**************************************************************
// Free up Element by writing to RBUF_ELEMENT_DONE{Channel}
//**************************************************************
alu[temp, --, B, elem, <<16]
msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
.if (error == 1)
immed[$scratch_data, RECEIVE_ERROR]
br[fill#]
.endif
alu[packet_size, packet_size, +, bytecnt]
.if (eopbit == 0)
br[next_packet#]
.endif
alu[$scratch_data, bdptr, OR, packet_size, <<24]
fill#:
br_inp_state[SCR_Ring0_Full, fill#]
scratch[put, $scratch_data, ring_num, 0, 1], ctx_swap[scratch_sig]
immed[packet_size, 0]
/*
.begin
.reg scratch_add $s_xfer
.sig scratch_sig
alu[packet_count, packet_count, +, 1]
immed[scratch_add, 0x400]
alu[$s_xfer, --, B, packet_count]
scratch[write, $s_xfer, scratch_add, 0, 1], ctx_swap[scratch_sig]
.end
*/
NULL#:
next_packet#:
br[ReceivePacket#] // loop around and wait for next packet
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