sys_loopback_bd_in_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.0.411
+uca_date: Sep  9 2002 00:25:20
+current_date: Fri Nov 01 15:47:30 2002

.cpu_version 0x00000002 0 15

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:cont1# 85
:fill# 122
:init# 2
:l000_01# 54
:l000_end# 54
:l001_01# 68
:l001_end# 75
:l002_01# 65
:l002_end# 67
:l003_01# 74
:l003_end# 75
:l004_01# 88
:l004_end# 88
:l005_01# 106
:l005_end# 106
:l006_01# 110
:l006_end# 110
:next_packet# 127
:transmit# 58
:wait_for_assignment# 45
*-- no_destination 0
;*l0000!temp!!2 gpr_b_rel 07
;*l0000!temp!!3 gpr_b_rel 07
;*l0000!temp!!4 gpr_b_rel 07
*l0000!temp gpr_b_rel 07
*l0000!t0 gpr_b_rel 00
*l0000!sramdescbase gpr_a_rel 00
*l0000!drampacketbase gpr_b_rel 01
;*l0000!pkt_buf_addr!!2 gpr_a_rel 01
;*l0000!pkt_buf_addr!!3 gpr_a_rel 01
*l0000!pkt_buf_addr gpr_b_rel 08
*l0000!loop_count gpr_b_rel 02
*l0000!put_ring_num gpr_b_rel 03
*l0000!get_ring_num gpr_a_rel 02
;*l0000!msfaddress!!2 gpr_b_rel 09
;*l0000!msfaddress!!3 gpr_a_rel 03
*l0000!msfaddress gpr_b_rel 09
*l0000!byte_count gpr_a_rel 04
*l0000!packet_count gpr_b_rel 04
*l0000!mask_qa gpr_a_rel 05
*l0000!packet_size gpr_a_rel 06
*l0000!packet_status gpr_b_rel 05
*l0000!sopeop gpr_b_rel 0A
*l0000!txconfigdata0 gpr_a_rel 09
*$l0000!txconfigdata0 sram_rel 01 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 01 0 both 2 0x23
*$l0000!txcontrolword1 sram_rel 02 0 both 1 0x23
*$l0000!scratch_data0 sram_rel 00 0 both 1 0x0
*l0000!tbuf_element gpr_a_rel 07
*l0000!tbuf gpr_b_rel 06
*$l0000!prepend_data0 sram_rel 00 0 both 2 0x1B
*$l0000!prepend_data1 sram_rel 01 0 both 1 0x1B
*$l0000!verbose sram_rel 01 0 both 1 0x0
*l0001!channel_number gpr_b_rel 00
*$l0002!scratch_base sram_rel 01 0 both 1 0x0
*$l0002!scratch_head sram_rel 02 0 both 1 0x0
*$l0002!scratch_tail sram_rel 03 0 both 1 0x0
*l0003!pci_base gpr_a_rel 0A
*l0003!pci_offset gpr_b_rel 0B
*l0004!__immed_big_const gpr_b_rel 0C
;*l0005!cur_tbuf_addr!!2 gpr_b_rel 0D
;*l0005!cur_tbuf_addr!!3 gpr_b_rel 0D
;*l0005!cur_tbuf_addr!!4 gpr_a_rel 08
*l0005!cur_tbuf_addr gpr_b_rel 0D
;*l0005!refcnt!!2 gpr_b_rel 0E
;*l0005!refcnt!!3 gpr_b_rel 0E
*l0005!refcnt gpr_b_rel 0E
;*l0006!temp!!2 gpr_a_rel 0B
*l0006!temp gpr_b_rel 0F
*l0006!cellcount gpr_b_rel 08
*l0006!buf_addr gpr_b_rel 0A
*$l0007!scratch_data sram_rel 01 0 both 1 0x0
*l0003!pci_sig signal 01 0
*l0002!scratch_sig3 signal 03 0
*l0002!scratch_sig3!!2 signal 03 0
*l0002!scratch_sig2 signal 02 0
*l0002!scratch_sig2!!2 signal 02 0
*l0002!scratch_sig1 signal 01 0
*l0002!scratch_sig1!!2 signal 01 0
*l0000!scratch_sig signal 01 0
*l0000!scratch_sig!!3 signal 01 0
*l0000!scratch_sig!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!dram_sig signal 02 0
.%type R
.%type SI
.%scope global
.%var $l0007!scratch_data 0 R
.%liverange 0 $W1 125:126
.%liverange 0 ~$W1 45:75 127:127
.%liverange 0 $R1 128:128
.%var l0006!buf_addr 0 R
.%liverange 0 B10 112:127
.%liverange 0 ~B10 45:63 65:66 68:72 74:74
.%var l0006!cellcount 0 R
.%liverange 0 B8 115:127
.%liverange 0 ~B8 45:54
.%var l0006!temp 0 R
.%liverange 0 B15 113:113
.%liverange 0 A11 114:127
.%liverange 0 ~A11 45:112
.%var l0005!refcnt 0 R
.%liverange 0 B14 82:127
.%liverange 0 ~B14 45:81
.%var l0005!cur_tbuf_addr 0 R
.%liverange 0 B13 77:80
.%liverange 0 A8 81:127
.%liverange 0 ~A8 45:76
.%var l0004!__immed_big_const 0 R
.%liverange 0 B12 49:127
.%liverange 0 ~B12 45:48
.%var l0003!pci_offset 0 R
.%liverange 0 B11 41:127
.%var l0003!pci_base 0 R
.%liverange 0 A10 39:127
.%var $l0002!scratch_tail 0 R
.%liverange 0 $W3 28:127
.%liverange 0 $R3 128:128
.%var $l0002!scratch_head 0 R
.%liverange 0 $W2 27:44
.%liverange 0 ~$W2 45:100
.%liverange 0 $R2 128:128
.%var $l0002!scratch_base 0 R
.%liverange 0 $W1 29:44
.%liverange 0 ~$W1 45:75
.%liverange 0 $R1 128:128
.%var l0001!channel_number 0 R
.%liverange 0 B0 16:16
.%var $l0000!verbose 0 R
.%liverange 0 $W1 128:128
.%liverange 0 $R1 42:127
.%var $l0000!prepend_data1 0 R
.%liverange 0 $W1 76:97
.%liverange 0 $R1 128:128
.%var $l0000!prepend_data0 0 R
.%liverange 0 $W0 9:51 54:127
.%liverange 0 $R0 128:128
.%var l0000!tbuf 0 R
.%liverange 0 B6 18:127
.%var l0000!tbuf_element 0 R
.%liverange 0 A7 5:127
.%var $l0000!scratch_data0 0 R
.%liverange 0 $W0 52:53
.%liverange 0 $R0 46:127
.%liverange 0 ~$R0 45:45
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W2 101:127
.%liverange 0 ~$W2 45:100
.%liverange 0 $R2 128:128
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W1 98:124
.%liverange 0 ~$W1 45:75 127:127
.%liverange 0 $R1 128:128
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W1 22:28
.%liverange 0 $R1 128:128
.%var l0000!txconfigdata0 0 R
.%liverange 0 A9 20:127
.%var l0000!sopeop 0 R
.%liverange 0 B10 64:64 67:67 73:73 75:111
.%liverange 0 ~B10 58:63 65:66 68:72 74:74
.%var l0000!packet_status 0 R
.%liverange 0 B5 8:127
.%var l0000!packet_size 0 R
.%liverange 0 A6 58:127
.%liverange 0 ~A6 45:57
.%var l0000!mask_qa 0 R
.%liverange 0 A5 3:127
.%var l0000!packet_count 0 R
.%liverange 0 B4 6:127
.%var l0000!byte_count 0 R
.%liverange 0 A4 63:64 66:67 69:127
.%liverange 0 ~A4 45:62 65:65 68:68
.%var l0000!msfaddress 0 R
.%liverange 0 B9 19:44 94:94
.%liverange 0 ~B9 45:93
.%liverange 0 A3 95:127
.%liverange 0 ~A3 45:93
.%var l0000!get_ring_num 0 R
.%liverange 0 A2 10:127
.%var l0000!put_ring_num 0 R
.%liverange 0 B3 11:127
.%var l0000!loop_count 0 R
.%liverange 0 B2 7:127
.%var l0000!pkt_buf_addr 0 R
.%liverange 0 B8 55:55
.%liverange 0 A1 56:127
.%liverange 0 ~A1 45:54
.%var l0000!drampacketbase 0 R
.%liverange 0 B1 14:127
.%var l0000!sramdescbase 0 R
.%liverange 0 A0 12:127
.%var l0000!t0 0 R
.%liverange 0 B0 17:127
.%var l0000!temp 0 R
.%liverange 0 B7 43:127
.%var l0003!pci_sig 1 R
.%liverange 0 G1 42:42
.%var l0002!scratch_sig3 1 R
.%liverange 0 G3 32:33 37:38
.%var l0002!scratch_sig2 1 R
.%liverange 0 G2 31:33 36:38
.%var l0002!scratch_sig1 1 R
.%liverange 0 G1 30:33 35:38
.%var l0000!scratch_sig 1 R
.%liverange 0 G1 46:46 53:53 126:127
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 128:128
.%var l0000!msf_sig 1 R
.%liverange 0 G1 23:23 26:26 78:78 102:102
.%var l0000!dram_sig 1 R
.%liverange 0 D2 92:93
.%scope end
.0 D800800010 common_code
	.import_var __chip_id __chip_revision __uengine_id
	.%line 65 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg l0000!temp $l0000!temp
	.%line 66 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg l0000!t0 l0000!sramdescbase l0000!drampacketbase l0000!pkt_buf_addr l0000!loop_count l0000!put_ring_num l0000!get_ring_num
	.%line 67 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg l0000!msfaddress l0000!msfaddress0 l0000!msfaddress1
	.%line 68 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg l0000!byte_count l0000!packet_count l0000!mask_qa l0000!packet_size l0000!packet_status l0000!sopeop
	.%line 69 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg l0000!txconfigdata0
	.%line 70 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg $l0000!txconfigdata0
	.%line 71 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 72 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg $l0000!scratch_data0
	.%line 73 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg l0000!tbuf_element
	.%line 74 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg l0000!dram_addr l0000!tbuf
	.%line 75 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg $l0000!prepend_data0 $l0000!prepend_data1
	.%line 76 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.reg $l0000!verbose
	.%line 78 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bd\sys_loopback_bd_in_tx.uc" 1 0
	.sig l0000!dram_sig l0000!msf_sig l0000!interthd_sig l0000!cap_sig l0000!scratch_sig