sys_loopback_bd_in_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.0.411
+uca_date: Sep  9 2002 00:25:20
+current_date: Fri Nov 01 15:47:29 2002

.cpu_version 0x00000002 0 15

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:addfreelist# 50
:cont1# 87
:context_enable_csr_config# 55
:fill# 106
:free_element# 95
:init_rbuf# 24
:init_value# 3
:l000_01# 80
:l000_end# 80
:l001_01# 90
:l001_end# 90
:l002_01# 101
:l002_end# 101
:l003_01# 105
:l003_end# 105
:next_packet# 109
:null# 109
:receivepacket# 65
:rsw# 67
*-- no_destination 0
*l0000!ring_num gpr_b_rel 00
*l0000!packet_size gpr_a_rel 00
*l0000!pkt_buff_addr gpr_b_rel 01
*l0000!bdptr gpr_b_rel 02
*$l0000!transferreg00 sram_rel 01 0 both 2 0x41
*$l0000!transferreg01 sram_rel 02 0 both 1 0x41
*$l0000!scratch_data sram_rel 01 0 both 1 0x0
*l0000!temp gpr_b_rel 03
*l0000!t0 gpr_a_rel 01
*l0000!packet_count gpr_b_rel 00
*l0000!rxthreadlist gpr_b_rel 0C
*l0000!sopbit gpr_b_rel 0E
*l0000!eopbit gpr_a_rel 02
*l0000!bytecnt gpr_b_rel 04
*l0000!elem gpr_a_rel 03
*$l0000!rxconfigdata sram_rel 00 0 both 1 0x0
*$l0000!rxconfigdata0 sram_rel 01 0 both 1 0x0
;*l0000!rxconfigdata0!!2 gpr_b_rel 0F
*l0000!rxconfigdata0 gpr_b_rel 0F
*l0000!rbuf gpr_b_rel 05
*l0000!scratch_addr gpr_b_rel 02
;*l0000!msfaddress!!2 gpr_b_rel 06
;*l0000!msfaddress!!3 gpr_b_rel 06
;*l0000!msfaddress!!4 gpr_b_rel 06
*l0000!msfaddress gpr_b_rel 06
*l0000!sramdescbase gpr_a_rel 04
*l0000!drampacketbase gpr_a_rel 05
*l0000!error gpr_b_rel 07
*l0000!rxupcontrol0 gpr_b_rel 03
*$l0000!sr0 sram_rel 00 0 both 4 0x1F
*$l0000!sr1 sram_rel 01 0 both 3 0x1F
*$l0000!sr2 sram_rel 02 0 both 2 0x1F
*$l0000!sr3 sram_rel 03 0 both 1 0x1F
*l0001!channel_number gpr_b_rel 05
*l0002!temp_reg gpr_b_rel 04
*l0002!temp gpr_b_rel 07
*l0003!cellcount gpr_b_rel 0A
*l0003!freelist gpr_b_rel 0B
*$l0003!s0 sram_rel 01 0 both 3 0x14
*$l0003!s1 sram_rel 02 0 both 2 0x14
*$l0003!s2 sram_rel 03 0 both 1 0x14
;*l0003!tmp!!2 gpr_b_rel 0C
;*l0003!tmp!!3 gpr_b_rel 0C
;*l0003!tmp!!4 gpr_b_rel 0C
*l0003!tmp gpr_b_rel 0C
*l0004!ctxenabledata gpr_b_rel 0D
*l0005!pci_base gpr_a_rel 07
*l0005!pci_offset gpr_b_rel 0A
*l0005!temp gpr_b_rel 0B
*$l0005!pci_rw sram_rel 01 0 both 1 0x0
;*l0006!cur_rbuf_addr!!2 gpr_b_rel 08
;*l0006!cur_rbuf_addr!!3 gpr_a_rel 06
*l0006!cur_rbuf_addr gpr_b_rel 08
;*l0006!refcnt!!2 gpr_b_rel 09
;*l0006!refcnt!!3 gpr_b_rel 09
*l0006!refcnt gpr_b_rel 09
*l0006!rel gpr_b_rel 0D
*l0006!freebuffer gpr_b_rel 01
*l0006!sig_free_buf signal 01 0
*l0005!pci_sig signal 01 0
*l0003!qa_init signal 01 0
*l0003!qa_init!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig_thd signal 02 0
*l0000!dram_sig signal 02 0
*l0000!scratch_sig signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var l0006!freebuffer 0 R
.%liverange 0 B1 77:79
.%var l0006!rel 0 R
.%liverange 0 B13 79:79
.%liverange 0 ~B13 65:78 80:109
.%var l0006!refcnt 0 R
.%liverange 0 B9 84:94
.%liverange 0 ~B9 65:83 95:109
.%var l0006!cur_rbuf_addr 0 R
.%liverange 0 B8 81:82
.%liverange 0 A6 83:94
.%liverange 0 ~A6 65:80 95:109
.%var $l0005!pci_rw 0 R
.%liverange 0 $W1 63:64
.%liverange 0 ~$W1 65:99 101:105 109:109
.%liverange 0 $R1 110:110
.%var l0005!temp 0 R
.%liverange 0 B11 62:109
.%var l0005!pci_offset 0 R
.%liverange 0 B10 61:109
.%var l0005!pci_base 0 R
.%liverange 0 A7 59:109
.%var l0004!ctxenabledata 0 R
.%liverange 0 B13 56:64
.%liverange 0 ~B13 65:78 80:109
.%var l0003!tmp 0 R
.%liverange 0 B12 39:109
.%var $l0003!s2 0 R
.%liverange 0 $W3 43:109
.%liverange 0 $R3 110:110
.%var $l0003!s1 0 R
.%liverange 0 $W2 42:109
.%liverange 0 $R2 110:110
.%var $l0003!s0 0 R
.%liverange 0 $W1 41:62
.%liverange 0 $R1 110:110
.%var l0003!freelist 0 R
.%liverange 0 B11 49:61
.%var l0003!cellcount 0 R
.%liverange 0 B10 50:60
.%var l0002!temp 0 R
.%liverange 0 B7 25:64
.%liverange 0 ~B7 24:24 65:71
.%var l0002!temp_reg 0 R
.%liverange 0 B4 24:64
.%liverange 0 ~B4 65:70
.%var l0001!channel_number 0 R
.%liverange 0 B5 10:15
.%var $l0000!sr3 0 R
.%liverange 0 $W3 110:110
.%liverange 0 $R3 110:110
.%var $l0000!sr2 0 R
.%liverange 0 $W2 110:110
.%liverange 0 $R2 110:110
.%var $l0000!sr1 0 R
.%liverange 0 $W1 110:110
.%liverange 0 $R1 110:110
.%var $l0000!sr0 0 R
.%liverange 0 $W0 110:110
.%liverange 0 $R0 47:109
.%var l0000!rxupcontrol0 0 R
.%liverange 0 B3 31:64
.%liverange 0 ~B3 65:95
.%var l0000!error 0 R
.%liverange 0 B7 72:109
.%liverange 0 ~B7 65:71
.%var l0000!drampacketbase 0 R
.%liverange 0 A5 12:109
.%var l0000!sramdescbase 0 R
.%liverange 0 A4 14:109
.%var l0000!msfaddress 0 R
.%liverange 0 B6 19:109
.%var l0000!scratch_addr 0 R
.%liverange 0 B2 4:7
.%var l0000!rbuf 0 R
.%liverange 0 B5 16:109
.%var l0000!rxconfigdata0 0 R
.%liverange 0 B15 20:109
.%var $l0000!rxconfigdata0 0 R
.%liverange 0 $W1 22:40
.%liverange 0 $R1 110:110
.%var $l0000!rxconfigdata 0 R
.%liverange 0 $W0 18:109
.%liverange 0 $R0 110:110
.%var l0000!elem 0 R
.%liverange 0 A3 68:109
.%liverange 0 ~A3 65:67
.%var l0000!bytecnt 0 R
.%liverange 0 B4 71:109
.%liverange 0 ~B4 65:70
.%var l0000!eopbit 0 R
.%liverange 0 A2 70:109
.%liverange 0 ~A2 65:69
.%var l0000!sopbit 0 R
.%liverange 0 B14 69:109
.%liverange 0 ~B14 65:68
.%var l0000!rxthreadlist 0 R
.%liverange 0 B12 17:38
.%var l0000!packet_count 0 R
.%liverange 0 B0 5:8
.%var l0000!t0 0 R
.%liverange 0 A1 11:109
.%var l0000!temp 0 R
.%liverange 0 B3 96:109
.%liverange 0 ~B3 65:95
.%var $l0000!scratch_data 0 R
.%liverange 0 $W1 100:100 106:108
.%liverange 0 ~$W1 65:99 101:105 109:109
.%liverange 0 $R1 110:110
.%var $l0000!transferreg01 0 R
.%liverange 0 $W2 110:110
.%liverange 0 $R2 110:110
.%var $l0000!transferreg00 0 R
.%liverange 0 $W1 0:21
.%liverange 0 $R1 0:109
.%var l0000!bdptr 0 R
.%liverange 0 B2 8:109
.%var l0000!pkt_buff_addr 0 R
.%liverange 0 B1 7:76 80:109
.%var l0000!packet_size 0 R
.%liverange 0 A0 6:109
.%var l0000!ring_num 0 R
.%liverange 0 B0 9:109
.%var l0006!sig_free_buf 1 R
.%liverange 0 G1 76:76
.%var l0005!pci_sig 1 R
.%liverange 0 G1 64:64
.%var l0003!qa_init 1 R
.%liverange 0 G1 44:44 47:47
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:1
.%var l0000!rx_sig_thd 1 R
.%liverange 0 G2 65:67
.%var l0000!dram_sig 1 R
.%liverange 0 D2 94:95
.%var l0000!scratch_sig 1 R
.%liverange 0 G1 108:108