sys_loopback_bd_2_eg_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:02:24 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:0xfbfb# 80
:init_rbuf# 35
:init_thread0_only# 20
:l000_01# 76
:l000_end# 77
:next_packet# 79
:null# 79
:receivenextpacket# 55
:rsw# 58
*-- no_destination 0
*l0000!cur_me gpr_a_rel 02
*l0000!cur_ctx gpr_b_rel 00
*l0000!sram_channel_number gpr_b_rel 09
*l0000!t0 gpr_b_rel 0A
*@l0000!total_rx gpr_a_abs 31
;*l0000!rxconfigdata!!2 gpr_a_rel 03
*l0000!rxconfigdata gpr_b_rel 0B
*l0000!rbuf_base gpr_a_rel 00
*l0000!rbuf_elem_done gpr_b_rel 0C
*l0000!rx_thd_freelist gpr_b_rel 01
*l0000!null gpr_b_rel 0D
*l0000!elem gpr_b_rel 02
*$l0000!sequence_count sram_rel 01 0 both 1 0x0
*$l0000!pkt_number sram_rel 00 0 both 1 0x0
*@l0000!sramdescbase gpr_a_abs 01
*@l0000!drampacketbase gpr_a_abs 11
*@l0000!expected_sequence_0 gpr_a_abs 21
*$l0000!transferreg00 sram_rel 00 0 both 2 0x28
*$l0000!transferreg01 sram_rel 01 0 both 1 0x28
*l0001!temp_data gpr_b_rel 0E
;*l0002!rxthreadlist!!2 gpr_a_rel 04
;*l0002!rxthreadlist!!3 gpr_b_rel 0F
*l0002!rxthreadlist gpr_a_rel 04
*l0002!temp_data gpr_a_rel 05
;*l0002!me_data!!2 gpr_b_rel 03
*l0002!me_data gpr_b_rel 03
*l0003!msfaddress gpr_b_rel 00
*l0003!rxcontroldata gpr_b_rel 02
*$l0003!rxcontroldata sram_rel 00 0 both 1 0x0
*l0004!msfaddress gpr_b_rel 04
*$l0004!csixtypemapdata sram_rel 00 0 both 1 0x0
*l0005!temp_reg gpr_b_rel 04
*l0005!rbufelemdonedata gpr_b_rel 05
*l0006!msfaddress gpr_b_rel 05
*$l0006!rxcontroldata sram_rel 01 0 both 1 0x0
;*l0007!timeout_val!!2 gpr_b_rel 06
*l0007!timeout_val gpr_b_rel 06
*$l0008!scratch_base sram_rel 00 0 both 1 0x0
*$l0008!scratch_head sram_rel 01 0 both 1 0x0
*$l0008!scratch_tail sram_rel 02 0 both 1 0x0
*l0008!temp_val gpr_b_rel 07
*l0009!temp_scratch_addr gpr_b_rel 08
*l0010!ind_ref_data gpr_b_rel 06
*l0011!rbufaddress gpr_b_rel 07
*l0012!temp_sequence gpr_b_rel 08
*l0013!rbuf_elem_done_data gpr_b_rel 09
*$l0014!temp_scratch sram_rel 00 0 both 2 0x3
*$l0014!pkt_num sram_rel 01 0 both 1 0x3
*l0014!temp_scratch_addr gpr_b_rel 01
*l0008!scratch_sig3 signal 03 0
*l0008!scratch_sig2 signal 02 0
*l0008!scratch_sig1 signal 01 0
*l0000!scratch_sig signal 02 0
*l0000!scratch_sig!!2 signal 02 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!next_ctx_sig signal 0E 0
*l0000!rx_sig signal 01 0
.%type R
.%type SI
.%scope global
.%var l0014!temp_scratch_addr 0 R
.%liverange 0 B1 83:84
.%var $l0014!pkt_num 0 R
.%liverange 0 $W1 81:84
.%liverange 0 $R1 85:85
.%var $l0014!temp_scratch 0 R
.%liverange 0 $W0 82:84
.%liverange 0 $R0 85:85
.%var l0013!rbuf_elem_done_data 0 R
.%liverange 0 B9 78:78
.%liverange 0 ~B9 55:77 79:84
.%var l0012!temp_sequence 0 R
.%liverange 0 B8 71:78 80:84
.%liverange 0 ~B8 55:62 79:79
.%var l0011!rbufaddress 0 R
.%liverange 0 B7 67:78 80:84
.%liverange 0 ~B7 55:66 79:79
.%var l0010!ind_ref_data 0 R
.%liverange 0 B6 69:78 80:84
.%liverange 0 ~B6 55:68 79:79
.%var l0009!temp_scratch_addr 0 R
.%liverange 0 B8 63:70
.%var l0008!temp_val 0 R
.%liverange 0 B7 48:54
.%liverange 0 ~B7 55:66 79:79
.%var $l0008!scratch_tail 0 R
.%liverange 0 $W2 51:54
.%liverange 0 ~$W2 55:84
.%liverange 0 $R2 85:85
.%var $l0008!scratch_head 0 R
.%liverange 0 $W1 50:54
.%liverange 0 ~$W1 55:80
.%liverange 0 $R1 85:85
.%var $l0008!scratch_base 0 R
.%liverange 0 $W0 49:54
.%liverange 0 ~$W0 55:61 79:79
.%liverange 0 $R0 85:85
.%var l0007!timeout_val 0 R
.%liverange 0 B6 45:54
.%liverange 0 ~B6 55:68 79:79
.%var $l0006!rxcontroldata 0 R
.%liverange 0 $W1 43:49
.%liverange 0 $R1 42:54
.%liverange 0 ~$R1 55:67 79:79
.%var l0006!msfaddress 0 R
.%liverange 0 B5 41:54
.%liverange 0 ~B5 55:84
.%var l0005!rbufelemdonedata 0 R
.%liverange 0 B5 36:40
.%liverange 0 ~B5 35:35
.%var l0005!temp_reg 0 R
.%liverange 0 B4 35:54
.%liverange 0 ~B4 55:84
.%var $l0004!csixtypemapdata 0 R
.%liverange 0 $W0 32:48
.%liverange 0 $R0 85:85
.%var l0004!msfaddress 0 R
.%liverange 0 B4 33:34
.%var $l0003!rxcontroldata 0 R
.%liverange 0 $W0 29:31
.%liverange 0 $R0 85:85
.%var l0003!rxcontroldata 0 R
.%liverange 0 B2 27:54
.%liverange 0 ~B2 55:64 79:79
.%var l0003!msfaddress 0 R
.%liverange 0 B0 30:54
.%liverange 0 ~B0 55:84
.%var l0002!me_data 0 R
.%liverange 0 B3 10:84
.%var l0002!temp_data 0 R
.%liverange 0 A5 11:84
.%var l0002!rxthreadlist 0 R
.%liverange 0 A4 13:14
.%liverange 0 B15 15:84
.%var l0001!temp_data 0 R
.%liverange 0 B14 2:84
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 85:85
.%liverange 0 $R1 85:85
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:28
.%liverange 0 ~$W0 55:61 79:79
.%liverange 0 $R0 0:84
.%var @l0000!expected_sequence_0 0 R
.%liverange 0 @A33 0:84
.%var @l0000!drampacketbase 0 R
.%liverange 0 @A17 0:84
.%var @l0000!sramdescbase 0 R
.%liverange 0 @A1 0:84
.%var $l0000!pkt_number 0 R
.%liverange 0 $W0 62:78 80:81
.%liverange 0 ~$W0 55:61 79:79
.%liverange 0 $R0 85:85
.%var $l0000!sequence_count 0 R
.%liverange 0 $W1 85:85
.%liverange 0 $R1 68:78 80:84
.%liverange 0 ~$R1 55:67 79:79
.%var l0000!elem 0 R
.%liverange 0 B2 65:78 80:84
.%liverange 0 ~B2 55:64 79:79
.%var l0000!null 0 R
.%liverange 0 B13 59:84
.%liverange 0 ~B13 55:58
.%var l0000!rx_thd_freelist 0 R
.%liverange 0 B1 9:82
.%var l0000!rbuf_elem_done 0 R
.%liverange 0 B12 8:84
.%var l0000!rbuf_base 0 R
.%liverange 0 A0 7:84
.%var l0000!rxconfigdata 0 R
.%liverange 0 B11 16:16
.%liverange 0 A3 17:84
.%var @l0000!total_rx 0 R
.%liverange 0 @A49 0:84
.%var l0000!t0 0 R
.%liverange 0 B10 6:84
.%var l0000!sram_channel_number 0 R
.%liverange 0 B9 5:54
.%liverange 0 ~B9 55:77 79:84
.%var l0000!cur_ctx 0 R
.%liverange 0 B0 4:29
.%liverange 0 ~B0 55:84
.%var l0000!cur_me 0 R
.%liverange 0 A2 3:84
.%var l0008!scratch_sig3 1 R
.%liverange 0 G3 54:55
.%var l0008!scratch_sig2 1 R