pl_media_lpbk-jumboframe_rx.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* pl_media_loopback_rx.uc
 *
 * This file receives a POS packet from the media and stores it to DRAM. Then
 * it signals the XScale indicating that it has received a packet.
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXDP2400
 *  subsystem: DIAG
 *  author: dalsraja, April, 2002
 *  revisions: dalsraja, May 8, 2002
 * 
 * 
 * --------------------------------------------------------------------------
 */

#include "common_uc.h"

#define RX_SINGLE_PHY					MSF_SINGLE_PHY
#define RX_WIDTH						MSF_WIDTH_4x8
#define RX_ENABLE_MASK					0xF
#define RX_MODE							MSF_POS_UTOPIA
#define RX_ELEMENTSIZE					MSF_ELEMENTSIZE_128
#define RBUF_ELEM_COUNT					(1 << (7 - RX_ELEMENTSIZE))
#define RBUF_ADDR_SHF					(6 + RX_ELEMENTSIZE)
#define RX_ELEMENT_SIZE_BYTE			(1 << RBUF_ADDR_SHF)

//#define_eval	UP_CTRL_PP_MODE			(MSF_POS3 << 5)
//#define_eval	UP_CTRL_PARITY			(MSF_PARITY_ODD << 2)

#define ME_NUM_RX						0

#define RX_TRANSFER_THREAD				&$TransferReg00
#define RX_SIGNAL_THREAD				&rx_sig_thd
#define INTERTHD_SIG_NUM				15

#define SRAM_DESC_BASE					0x200000		// 2 Meg onwards
#define DRAM_PCKT_BASE					0x1000000
#define SCRATCH_MSG_BASE				0x1000
#define PORT_BUFFER_SIZE				0x8000
#define PORT0_BUFF						0xC0080000
#define PORT1_BUFF						0xC0080100
#define PORT2_BUFF						0xC0080200
#define PORT3_BUFF						0xC0080300

.reg $TransferReg00 $TransferReg01
.reg RxThreadList bytecnt elem error rx_channel_num sopeop
.reg buf total_bytes_rx
.reg RxConfigData buffer_consumed cur_ctx
.reg rbuf ring_num
.reg MsfAddress ThreadFreelist_Addr ElementDone_Addr
.reg dramPacketBase
.reg sramDescBase counter
.reg sram_channel_number t0
.reg freebuffer rel pkt_buff_addr $sr0 sram_descriptor
.sig msf_sig dram_sig sram_sig
.sig rx_sig_thd interthd_sig
.xfer_order $TransferReg00 $TransferReg01

.addr interthd_sig INTERTHD_SIG_NUM

.set $TransferReg00
.set_sig interthd_sig

Init_Value#:
	br!=ctx[0, not_ctx_0#]
	immed[ThreadFreelist_Addr, RX_THREAD_FREELIST_0]
	br[cont_init1#]
not_ctx_0#:
	br!=ctx[1, not_ctx_1#]
	immed[ThreadFreelist_Addr, RX_THREAD_FREELIST_1]
	br[cont_init1#]
not_ctx_1#:
	br!=ctx[2, not_ctx_2#]
	immed[ThreadFreelist_Addr, RX_THREAD_FREELIST_2]
	br[cont_init1#]
not_ctx_2#:
	br!=ctx[3, not_ctx_3#]
	immed[ThreadFreelist_Addr, RX_THREAD_FREELIST_3]
	br[cont_init1#]
not_ctx_3#:
	ctx_arb[kill]

cont_init1#:
.begin
	.reg temp cur_me 
	local_csr_rd[ACTIVE_CTX_STS]
	immed[temp, 0]
	immed[buffer_consumed,0]
	immed[freebuffer,0]
	immed[buf, 0]
	immed_w1[buf,0xC008]
	alu[cur_me, MASK_4BIT, AND, temp, >>3]	// Extract the current ME number
	alu[cur_ctx, MASK_3BIT, AND, temp]		// Extract the current context number

	immed[total_bytes_rx, 0]
	immed[counter,0x2000]
	immed[sram_descriptor,0xBAD]

	immed[dramPacketBase, (DRAM_PCKT_BASE & MASK_16BIT)]
	immed_w1[dramPacketBase, ((DRAM_PCKT_BASE >> 16) & MASK_16BIT)]

	immed[sramDescBase, (SRAM_DESC_BASE & MASK_16BIT)]
	immed_w1[sramDescBase, ((SRAM_DESC_BASE >> 16) & MASK_16BIT)]

	alu[sram_channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
	alu[sram_descriptor, buf, OR, cur_ctx, <<8]

	immed[RxThreadList, (RX_SIGNAL_THREAD << 12)]
	alu[RxThreadList, RxThreadList, OR, cur_me, <<7]
	alu[RxThreadList, RxThreadList, OR, cur_ctx, <<4]
	alu[RxConfigData, RxThreadList,  OR , RX_TRANSFER_THREAD]
	alu[RxConfigData, --,  B, RxConfigData, <<16]
.end

	immed[ElementDone_Addr, RBUF_ELEMENT_DONE]
	immed[rbuf, RBUF_TBUF ]

	alu[ring_num, --, B, RING_0, <<2]			// ring number in a register

	br=ctx[0, cont_init2#]
	ctx_arb[interthd_sig]
	br[ReceivePacket#]


cont_init2#:
//****************************************************
// Configure RX/TX Control
//****************************************************
.begin
	.reg RxConfigData0 $RxConfigData0
	immed[RxConfigData0, ((0<<9) | (RX_ELEMENTSIZE << 2))]
	immed_w1[RxConfigData0, ((RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
	alu[$RxConfigData0, --, B, RxConfigData0]
	immed[MsfAddress, MSF_RX_CONTROL]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end


//******************************************************
// Initialize RBUF Freelist to add elements to the list
//******************************************************
.begin
	.reg temp_reg temp

	immed[temp_reg, 0]

init_RBUF#:
	alu[temp, --, B, temp_reg, <<16]
	msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
	alu[temp_reg, temp_reg, +, 1]
	alu[--, RBUF_ELEM_COUNT, -, temp_reg]
	bne[init_RBUF#]
.end


//******************************************************
// Configure RX UP Control CSRs 
//******************************************************
.begin
	.reg RxUPControl $RxConfigData0
	//immed[RxUPControl, (UP_CTRL_PP_MODE | UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
	immed[RxUPControl, (UP_CTRL_PP_MODE_PLONE | UP_CTRL_CP_MODE | UP_CTRL_PARITY_ODD | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
	alu[$RxConfigData0, --, B, RxUPControl]
	immed[MsfAddress, RX_UP_CONTROL_0]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
	immed[MsfAddress, RX_UP_CONTROL_1]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
	immed[MsfAddress, RX_UP_CONTROL_2]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
	immed[MsfAddress, RX_UP_CONTROL_3]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end


//****************************************************
// Configure RX/TX Control
//****************************************************
.begin
	.reg RxConfigData0 $RxConfigData0
	immed[RxConfigData0, ((0<<9) | (RX_ELEMENTSIZE << 2))]
	immed_w1[RxConfigData0, ((RX_ENABLE_MASK << 12) | (RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
	alu[$RxConfigData0, --, B, RxConfigData0]
	immed[MsfAddress, MSF_RX_CONTROL]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end


//**************************************************
// Configure Scratch Ring
//**************************************************
.begin
	.reg $scratch_base $scratch_head $scratch_tail
	.sig scratch_sig1 scratch_sig2 scratch_sig3

	immed[$scratch_head,0]
	immed[$scratch_tail,0]

	alu[$scratch_base, --, B, 0x3, <<30]	// Use ring size of 1024 lw and base 0x0
	cap[write, $scratch_base, SCRATCH_RING_BASE_0],sig_done[scratch_sig1]
	cap[write, $scratch_head, SCRATCH_RING_HEAD_0],sig_done[scratch_sig2]
	cap[write, $scratch_tail, SCRATCH_RING_TAIL_0],sig_done[scratch_sig3]
	ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
.end


//*****************************************************************
//  Write to MAILBOX3 register to indicate init complete
//*****************************************************************
#ifndef WORKBENCH_SIM
.begin
	.reg pci_base pci_offset $pci_rw
	.sig pci_sig

	immed[pci_base, (PCI_LOCAL_CSR_BASE & MASK_16BIT)]
	immed_w1[pci_base, ((PCI_LOCAL_CSR_BASE >> 16) & MASK_16BIT)]
	immed[pci_offset, MAILBOX3_OFFSET]
	immed[$pci_rw, INIT_COMPLETE]
	pci[write, $pci_rw, pci_base, pci_offset, 1], ctx_swap[pci_sig]
.end
#endif

	local_csr_wr[SAME_ME_SIGNAL, ((INTERTHD_SIG_NUM << 3) | 1)]
	local_csr_wr[SAME_ME_SIGNAL, ((INTERTHD_SIG_NUM << 3) | 2)]
	local_csr_wr[SAME_ME_SIGNAL, ((INTERTHD_SIG_NUM << 3) | 3)]


//********************************************************
// Start of Test	
//********************************************************
ReceivePacket#:
	.set_sig rx_sig_thd
	msf[fast_wr, --, ThreadFreelist_Addr, RxConfigData] // add thread to freelist
	ctx_arb[rx_sig_thd]
	

// RSW should be in xfer register
// Transfer RBUF data to sram_in transfer registers
//***************************************
// Extract RSW
//****************************************
.set pkt_buff_addr freebuffer
RSW#:
	alu[error, 0xF, AND, $TransferReg00, >>10]		// Extract error information
	beq[no_error#]

	ctx_arb[kill]

no_error#:
	alu[elem, --, B, $TransferReg00, >>24]			// Get element number
	alu[bytecnt, 0xFF, AND, $TransferReg00, >>16]	// Extract byte count
	alu[rx_channel_num, 0xF, AND, $TransferReg00]	// Extract channel

	alu[sopeop, 0x3, AND, $TransferReg00, >>14]

continue#:
	alu[--, sopeop, -, SOP_EOP]
	beq[proc_sop_eop#]
	alu[--, sopeop, -, SOP_NOEOP]
	beq[proc_sop_noeop#]
	alu[--, sopeop, -, NOSOP_EOP]
	beq[proc_nosop_eop#]
	alu[--, sopeop, -, MOP]
	beq[proc_mop#]

proc_sop_eop#:
proc_sop_noeop#:
	.if (total_bytes_rx > 0)
		// Error
	.endif

	alu[freebuffer, --, B, sram_descriptor, <<2]	
	alu[rel, freebuffer, -, sramDescBase]
	alu[rel, --, B, rel, <<12]
	alu[pkt_buff_addr, dramPacketBase, +, rel]

	br[store_mpacket#]

proc_nosop_eop#:
proc_mop#:
	alu[--, total_bytes_rx, -, 0]
	bne[store_mpacket#]
	// Error code here

store_mpacket#:

//*********************************
// Transfer from ME to DRAM
//*********************************	
.begin
	.reg rel RBufOffset refcnt temp

	alu[refcnt, --, B, bytecnt, >>3]
	alu[--, bytecnt, AND, 0x7]
	bne[set_refcnt_overwrite_bit#]
	alu[refcnt, refcnt, -, 1]

set_refcnt_overwrite_bit#:
	alu[refcnt, refcnt, OR, 1, <<4]		// Set the overwrite bit for refcnt
	alu[RBufOffset, --, B, elem, <<7]	// 128B
	alu[temp, RBuf, +, RBufOffset]
	alu[temp, 16, OR, temp, <<5]		// shift rbuf addr and set the overwrite bit
	alu[temp, temp, OR, refcnt, <<21]	// shift refcnt and add for indirect ref

	dram[rbuf_rd, --, pkt_buff_addr, total_bytes_rx, 8], indirect_ref, sig_done[dram_sig]
	ctx_arb[dram_sig]
.end


//**************************************************************
//  Free up Element by writing to RBUF_Element_Done
//**************************************************************
.begin
	.reg $temp0
	alu[$temp0, --, B, elem]
	msf[write, $temp0, ElementDone_Addr,0, 1], ctx_swap[msf_sig]
.end

	alu[total_bytes_rx, total_bytes_rx, +, bytecnt]

	alu[--, sopeop, AND, 0x1]
	beq[cont_rcv#]

is_eop#:
//*****************************************************************
//  Write to Scratch ring to signal completion to XScale code
//*****************************************************************

#ifndef WORKBENCH_SIM
.begin
	.reg $scratch_data $sram_data temp temp_addr $temp_val0
	.sig scratch_sig

	alu[$sram_data, total_bytes_rx, OR, rx_channel_num, <<24]
	sram[write, $sram_data, freebuffer, sram_channel_number, 1], ctx_swap[sram_sig]
//	alu[$temp_val0, total_bytes_rx, OR, rx_channel_num, <<24]

//	alu[$scratch_data, --, B, pkt_buff_addr]
	alu[$scratch_data, --, B, sram_descriptor]
	scratch[put, $scratch_data, ring_num, 0, 1], ctx_swap[scratch_sig]
.end
#endif


.begin
.reg tmp mask

	immed[mask,0xFCFF]
	immed_w1[mask,0xFFFF]
	alu[mask,mask,OR,cur_ctx,<<8]
	alu[tmp,sram_descriptor,+,1]
	alu[sram_descriptor,tmp,AND, mask]
.end

	immed[total_bytes_rx, 0]
cont_rcv#:
	br[ReceivePacket#]