media-lpbk-jumbo-frame.dwp

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

# Developer Workbench Project File
# Format Version 31.80
#********  Do not edit this file ***********

# Begin Project media-lpbk-jumbo-frame
CHIP_TYPE = 7
DEBUG_ONLY = FALSE
PROJECT_PATH = C:\diag\test_suites\microcode\media-lpbk-jumbo-frame\
MIN_REVISION_NUM = 0
MAX_REVISION_NUM = -1
ASSEMBLER_INCLUDE = ..\include\

# Begin Group Source Files

# Begin Source File
PATH = ..\include\common_uc.h
# End Source File

# Begin Source File
PATH = .\pl_media_lpbk-jumboFrame_rx.uc
# End Source File

# Begin Source File
PATH = .\pl_media_lpbk-jumboFrame_tx.uc
# End Source File
# End Group Source Files

# Begin Group Script Files

# Begin Script File
PATH = .\init_dram.ind
# End Script File

# Begin Script File
PATH = .\init_dram_pktspan.ind
# End Script File

# Begin Script File
PATH = .\start_receive.ind
# End Script File
# End Group Script Files

# Begin Debug Startup Options
DO_MODEL_INIT = TRUE
SIM_STEP_UNIT = Core
# End Debug Startup Options

# Begin Chip ingress

# Begin Chip Configuration Info

# Begin Clock Frequencies
USE_STANDARD_FREQ = TRUE
STANDARD_FREQ_INDEX = 1
CUSTOM_CLK_FREQ = 1200
SRAM0_DIVISOR = 0
SRAM1_DIVISOR = 0
DRAM_DIVISOR = 0
PCI_BUS_CLK_FREQ = 66
MSF_CCR = 0x00ff0000
# End Clock Frequencies

# Begin Memory Configuration Info
DRAM_SIZE = 64
SRAM_CHANNEL0_PART_COUNT = 1
SRAM_CHANNEL0_PART_SIZE = 64
SRAM_CHANNEL1_PART_COUNT = 1
SRAM_CHANNEL1_PART_SIZE = 64
# End Memory Configuration Info
# End Chip Configuration Info

# Begin MicroEngine 0
# End MicroEngine

# Begin MicroEngine 1
# End MicroEngine

# Begin MicroEngine 2
# End MicroEngine

# Begin MicroEngine 3
# End MicroEngine

# Begin MicroEngine 4
# End MicroEngine

# Begin MicroEngine 5
# End MicroEngine

# Begin MicroEngine 6
# End MicroEngine

# Begin MicroEngine 7
# End MicroEngine
# End Chip

# Begin Chip egress

# Begin Chip Configuration Info

# Begin Clock Frequencies
USE_STANDARD_FREQ = TRUE
STANDARD_FREQ_INDEX = 1
CUSTOM_CLK_FREQ = 1200
SRAM0_DIVISOR = 0
SRAM1_DIVISOR = 0
DRAM_DIVISOR = 0
PCI_BUS_CLK_FREQ = 66
MSF_CCR = 0x00ff0000
# End Clock Frequencies

# Begin Memory Configuration Info
DRAM_SIZE = 64
SRAM_CHANNEL0_PART_COUNT = 1
SRAM_CHANNEL0_PART_SIZE = 64
SRAM_CHANNEL1_PART_COUNT = 1
SRAM_CHANNEL1_PART_SIZE = 64
# End Memory Configuration Info
# End Chip Configuration Info

# Begin MicroEngine 0
# End MicroEngine

# Begin MicroEngine 1
# End MicroEngine

# Begin MicroEngine 2
# End MicroEngine

# Begin MicroEngine 3
# End MicroEngine

# Begin MicroEngine 4
# End MicroEngine

# Begin MicroEngine 5
# End MicroEngine

# Begin MicroEngine 6
# End MicroEngine

# Begin MicroEngine 7
# End MicroEngine
# End Chip

# Begin Assembler Settings
ASSEMBLY_REQUIRED = FALSE
ROOT_FILE = .\pl_media_lpbk-jumboFrame_rx.uc
OPTIMIZE = 0
WARNING_LEVEL = 3
CONVERT_WARNINGS = FALSE
REQUIRE_REG_DECLARATIONS = TRUE
CASE_SENSITIVE = TRUE
DEBUG_INFO = TRUE
OUTPUT = .\pl_media_lpbk-jumboFrame_rx.list
LOCAL_MEMORY_START = 0
ADDITIONAL_OPTIONS = 
# End Assembler Settings

# Begin Assembler Settings
ASSEMBLY_REQUIRED = FALSE
ROOT_FILE = .\pl_media_lpbk-jumboFrame_tx.uc
OPTIMIZE = 0
WARNING_LEVEL = 3
CONVERT_WARNINGS = FALSE
REQUIRE_REG_DECLARATIONS = TRUE
CASE_SENSITIVE = TRUE
DEBUG_INFO = TRUE
OUTPUT = .\pl_media_lpbk-jumboFrame_tx.list
LOCAL_MEMORY_START = 0
ADDITIONAL_OPTIONS = 
# End Assembler Settings

# Begin Linker Settings
LINK_REQUIRED = FALSE
CHIP_NAME = ingress
OUTPUT = .\ingress
DEBUG_INFO = TRUE
GEN_HEX_C_FILE = FALSE
SCRATCH_BASE_ADDR = 0x00000004
SCRATCH_SIZE = 0x00003ffc
SDRAM_BASE_ADDR = 0x00000010
SDRAM_SIZE = 0x7ffffff0
SRAM_BANK0_BASE_ADDR = 0x00000004
SRAM_BANK0_SIZE = 0x03fffffc
SRAM_BANK1_BASE_ADDR = 0x00000004
SRAM_BANK1_SIZE = 0x03fffffc
SRAM_BANK2_BASE_ADDR = 0x00000004
SRAM_BANK2_SIZE = 0x03fffffc
SRAM_BANK3_BASE_ADDR = 0x00000004
SRAM_BANK3_SIZE = 0x03fffffc
GEN_SEG_H_FILE = FALSE
GEN_MEM_MAP_FILE = FALSE
MAP_FILE = .\media-lpbk-jumbo-frame_ingress
# Begin Linker Map
MICROENGINE_NUMBER = 0
MICROENGINE_LIST_FILE = .\pl_media_lpbk-jumboFrame_rx.list
# End Linker Map
# End Linker Settings

# Begin Linker Settings
LINK_REQUIRED = FALSE
CHIP_NAME = egress
OUTPUT = .\egress
DEBUG_INFO = TRUE
GEN_HEX_C_FILE = FALSE
SCRATCH_BASE_ADDR = 0x00000004
SCRATCH_SIZE = 0x00003ffc
SDRAM_BASE_ADDR = 0x00000010
SDRAM_SIZE = 0x7ffffff0
SRAM_BANK0_BASE_ADDR = 0x00000004
SRAM_BANK0_SIZE = 0x03fffffc
SRAM_BANK1_BASE_ADDR = 0x00000004
SRAM_BANK1_SIZE = 0x03fffffc
SRAM_BANK2_BASE_ADDR = 0x00000004
SRAM_BANK2_SIZE = 0x03fffffc
SRAM_BANK3_BASE_ADDR = 0x00000004
SRAM_BANK3_SIZE = 0x03fffffc
GEN_SEG_H_FILE = FALSE
GEN_MEM_MAP_FILE = FALSE
MAP_FILE = .\media-lpbk-jumbo-frame_egress
# Begin Linker Map
MICROENGINE_NUMBER = 0
MICROENGINE_LIST_FILE = .\pl_media_lpbk-jumboFrame_tx.list
# End Linker Map
# End Linker Settings
# End Project