pl_media_lpbk-jumboframe_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.0.439
+uca_date: Oct  7 2002 00:17:47
+current_date: Tue May 13 13:28:33 2003

.cpu_version 0x00000002 0 15

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:cont_init1# 13
:cont_init2# 41
:cont_rcv# 134
:continue# 91
:init_rbuf# 47
:init_value# 0
:is_eop# 124
:l000_01# 101
:l000_end# 101
:no_error# 87
:not_ctx_0# 3
:not_ctx_1# 6
:not_ctx_2# 9
:not_ctx_3# 12
:proc_mop# 106
:proc_nosop_eop# 106
:proc_sop_eop# 99
:proc_sop_noeop# 99
:receivepacket# 82
:rsw# 84
:set_refcnt_overwrite_bit# 112
:store_mpacket# 108
*-- no_destination 0
*$l0000!transferreg00 sram_rel 00 0 both 2 0x4B
*$l0000!transferreg01 sram_rel 01 0 both 1 0x4B
;*l0000!rxthreadlist!!2 gpr_a_rel 0C
;*l0000!rxthreadlist!!3 gpr_b_rel 0A
*l0000!rxthreadlist gpr_a_rel 0C
*l0000!bytecnt gpr_b_rel 00
*l0000!elem gpr_a_rel 00
*l0000!error gpr_b_rel 0D
*l0000!rx_channel_num gpr_b_rel 01
*l0000!sopeop gpr_b_rel 02
*l0000!buf gpr_a_rel 0D
*l0000!total_bytes_rx gpr_a_rel 01
;*l0000!rxconfigdata!!2 gpr_a_rel 02
*l0000!rxconfigdata gpr_b_rel 0D
*l0000!buffer_consumed gpr_b_rel 0E
*l0000!cur_ctx gpr_b_rel 03
*l0000!rbuf gpr_a_rel 03
*l0000!ring_num gpr_a_rel 04
;*l0000!msfaddress!!2 gpr_b_rel 00
;*l0000!msfaddress!!3 gpr_b_rel 00
;*l0000!msfaddress!!4 gpr_b_rel 00
;*l0000!msfaddress!!5 gpr_b_rel 00
;*l0000!msfaddress!!6 gpr_b_rel 00
*l0000!msfaddress gpr_b_rel 00
*l0000!threadfreelist_addr gpr_b_rel 04
*l0000!elementdone_addr gpr_b_rel 05
*l0000!drampacketbase gpr_a_rel 05
*l0000!sramdescbase gpr_a_rel 06
*l0000!counter gpr_b_rel 08
*l0000!sram_channel_number gpr_a_rel 07
;*l0000!freebuffer!!2 gpr_b_rel 06
*l0000!freebuffer gpr_b_rel 06
;*l0000!rel!!2 gpr_b_rel 0C
*l0000!rel gpr_b_rel 0C
*l0000!pkt_buff_addr gpr_b_rel 07
;*l0000!sram_descriptor!!2 gpr_b_rel 08
*l0000!sram_descriptor gpr_b_rel 08
*l0001!temp gpr_b_rel 03
*l0001!cur_me gpr_b_rel 05
*l0002!rxconfigdata0 gpr_b_rel 01
*$l0002!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0003!temp_reg gpr_b_rel 0E
*l0003!temp gpr_b_rel 0F
*l0004!rxupcontrol gpr_b_rel 02
*$l0004!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0005!rxconfigdata0 gpr_b_rel 06
*$l0005!rxconfigdata0 sram_rel 00 0 both 1 0x0
*$l0006!scratch_base sram_rel 00 0 both 1 0x0
*$l0006!scratch_head sram_rel 01 0 both 1 0x0
*$l0006!scratch_tail sram_rel 02 0 both 1 0x0
*l0007!pci_base gpr_a_rel 09
*l0007!pci_offset gpr_b_rel 07
*$l0007!pci_rw sram_rel 00 0 both 1 0x0
*l0008!rbufoffset gpr_b_rel 09
;*l0008!refcnt!!2 gpr_a_rel 08
*l0008!refcnt gpr_b_rel 0A
;*l0008!temp!!2 gpr_b_rel 0B
;*l0008!temp!!3 gpr_b_rel 0B
*l0008!temp gpr_b_rel 0B
*$l0009!temp0 sram_rel 00 0 both 1 0x0
*$l0010!scratch_data sram_rel 00 0 both 1 0x0
*$l0010!sram_data sram_rel 00 0 both 1 0x0
*l0011!tmp gpr_a_rel 0A
;*l0011!mask!!2 gpr_b_rel 09
*l0011!mask gpr_a_rel 0B
*l0010!scratch_sig signal 01 0
*l0007!pci_sig signal 01 0
*l0006!scratch_sig3 signal 03 0
*l0006!scratch_sig2 signal 02 0
*l0006!scratch_sig1 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig_thd signal 01 0
*l0000!sram_sig signal 01 0
*l0000!dram_sig signal 02 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var l0011!mask 0 R
.%liverange 0 A11 129:130
.%liverange 0 B9 131:133
.%liverange 0 ~B9 82:113 134:134
.%var l0011!tmp 0 R
.%liverange 0 A10 132:133
.%liverange 0 ~A10 82:131 134:134
.%var $l0010!sram_data 0 R
.%liverange 0 $W0 125:126
.%liverange 0 $R0 135:135
.%var $l0010!scratch_data 0 R
.%liverange 0 $W0 127:133
.%liverange 0 ~$W0 82:119 134:134
.%liverange 0 $R0 135:135
.%var $l0009!temp0 0 R
.%liverange 0 $W0 120:124
.%liverange 0 ~$W0 82:119 134:134
.%liverange 0 $R0 135:135
.%var l0008!temp 0 R
.%liverange 0 B11 115:134
.%liverange 0 ~B11 82:114
.%var l0008!refcnt 0 R
.%liverange 0 B10 109:112
.%liverange 0 A8 113:134
.%liverange 0 ~A8 82:108
.%var l0008!rbufoffset 0 R
.%liverange 0 B9 114:130
.%liverange 0 ~B9 82:113 134:134
.%var $l0007!pci_rw 0 R
.%liverange 0 $W0 78:81
.%liverange 0 ~$W0 82:119
.%liverange 0 $R0 135:135
.%var l0007!pci_offset 0 R
.%liverange 0 B7 77:81
.%liverange 0 ~B7 82:83
.%var l0007!pci_base 0 R
.%liverange 0 A9 75:81
.%liverange 0 ~A9 82:134
.%var $l0006!scratch_tail 0 R
.%liverange 0 $W2 69:81
.%liverange 0 ~$W2 82:134
.%liverange 0 $R2 135:135
.%var $l0006!scratch_head 0 R
.%liverange 0 $W1 68:81
.%liverange 0 ~$W1 82:134
.%liverange 0 $R1 135:135
.%var $l0006!scratch_base 0 R
.%liverange 0 $W0 70:77
.%liverange 0 $R0 135:135
.%var $l0005!rxconfigdata0 0 R
.%liverange 0 $W0 65:69
.%liverange 0 $R0 135:135
.%var l0005!rxconfigdata0 0 R
.%liverange 0 B6 63:81
.%liverange 0 ~B6 82:83
.%var $l0004!rxconfigdata0 0 R
.%liverange 0 $W0 54:64
.%liverange 0 $R0 135:135
.%var l0004!rxupcontrol 0 R
.%liverange 0 B2 53:81
.%liverange 0 ~B2 82:90
.%var l0003!temp 0 R
.%liverange 0 B15 48:81
.%liverange 0 ~B15 47:47 82:134
.%var l0003!temp_reg 0 R
.%liverange 0 B14 47:81
.%liverange 0 ~B14 82:134
.%var $l0002!rxconfigdata0 0 R
.%liverange 0 $W0 44:53
.%liverange 0 $R0 135:135
.%var l0002!rxconfigdata0 0 R
.%liverange 0 B1 42:81
.%liverange 0 ~B1 82:89
.%var l0001!cur_me 0 R
.%liverange 0 B5 20:35
.%var l0001!temp 0 R
.%liverange 0 B3 15:20
.%var l0000!sram_descriptor 0 R
.%liverange 0 B8 24:134
.%var l0000!pkt_buff_addr 0 R
.%liverange 0 B7 84:134
.%liverange 0 ~B7 82:83
.%var l0000!rel 0 R
.%liverange 0 B12 103:105
.%liverange 0 ~B12 82:102 106:134
.%var l0000!freebuffer 0 R
.%liverange 0 B6 17:62 84:134
.%liverange 0 ~B6 82:83
.%var l0000!sram_channel_number 0 R
.%liverange 0 A7 29:134
.%var l0000!counter 0 R
.%liverange 0 B8 23:23
.%var l0000!sramdescbase 0 R
.%liverange 0 A6 27:134
.%var l0000!drampacketbase 0 R
.%liverange 0 A5 25:134
.%var l0000!elementdone_addr 0 R
.%liverange 0 B5 36:134
.%var l0000!threadfreelist_addr 0 R
.%liverange 0 B4 2:2 5:5 8:8 11:11 13:134
.%var l0000!msfaddress 0 R
.%liverange 0 B0 45:81
.%liverange 0 ~B0 82:88
.%var l0000!ring_num 0 R
.%liverange 0 A4 38:134
.%var l0000!rbuf 0 R
.%liverange 0 A3 37:134
.%var l0000!cur_ctx 0 R
.%liverange 0 B3 21:134
.%var l0000!buffer_consumed 0 R
.%liverange 0 B14 16:46
.%liverange 0 ~B14 82:134
.%var l0000!rxconfigdata 0 R
.%liverange 0 B13 34:34
.%liverange 0 A2 35:134
.%var l0000!total_bytes_rx 0 R
.%liverange 0 A1 22:134
.%var l0000!buf 0 R
.%liverange 0 A13 18:134
.%var l0000!sopeop 0 R
.%liverange 0 B2 91:134
.%liverange 0 ~B2 82:90
.%var l0000!rx_channel_num 0 R
.%liverange 0 B1 90:134
.%liverange 0 ~B1 82:89
.%var l0000!error 0 R
.%liverange 0 B13 85:134
.%liverange 0 ~B13 82:84
.%var l0000!elem 0 R
.%liverange 0 A0 88:134
.%liverange 0 ~A0 82:87
.%var l0000!bytecnt 0 R
.%liverange 0 B0 89:134
.%liverange 0 ~B0 82:88
.%var l0000!rxthreadlist 0 R
.%liverange 0 A12 31:32
.%liverange 0 B10 33:81
.%liverange 0 ~B10 82:108
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 135:135
.%liverange 0 $R1 135:135
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:43
.%liverange 0 ~$W0 82:119
.%liverange 0 $R0 0:134
.%var l0010!scratch_sig 1 R
.%liverange 0 G1 128:128
.%var l0007!pci_sig 1 R
.%liverange 0 G1 79:79
.%var l0006!scratch_sig3 1 R
.%liverange 0 G3 73:74
.%var l0006!scratch_sig2 1 R
.%liverange 0 G2 72:74
.%var l0006!scratch_sig1 1 R
.%liverange 0 G1 71:74
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:11 13:40
.%var l0000!rx_sig_thd 1 R
.%liverange 0 G1 82:84
.%var l0000!sram_sig 1 R
.%liverange 0 G1 126:126
.%var l0000!dram_sig 1 R
.%liverange 0 D2 118:119
.%var l0000!msf_sig 1 R
.%liverange 0 G1 46:46 56:56 58:58 60:60 62:62 67:67 121:121
.%scope end
.0 D800C00011 common_code