sys_loopback_bw_in_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.0.411
+uca_date: Sep  9 2002 00:25:20
+current_date: Tue Oct 29 18:44:35 2002

.cpu_version 0x00000002 0 15

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:addfreelist# 82
:cont1# 117
:cont_init# 41
:fill# 133
:init_rbuf# 47
:init_value# 6
:l000_01# 31
:l000_02# 35
:l000_03# 39
:l000_end# 40
:l001_01# 110
:l001_end# 110
:l002_01# 120
:l002_end# 120
:l003_01# 131
:l003_end# 131
:next_packet# 136
:receivepacket# 96
:rsw# 98
*-- no_destination 0
*l0000!cur_me gpr_a_rel 08
*l0000!cur_ctx gpr_a_rel 09
*l0000!threadfreelist_addr gpr_a_rel 00
*l0000!ring_num gpr_b_rel 00
*l0000!packet_size gpr_a_rel 01
*l0000!pkt_buff_addr gpr_b_rel 01
*l0000!bdptr gpr_b_rel 02
*$l0000!transferreg00 sram_rel 01 0 both 2 0x49
*$l0000!transferreg01 sram_rel 02 0 both 1 0x49
*$l0000!scratch_data sram_rel 00 0 both 1 0x0
*l0000!t0 gpr_a_rel 02
*l0000!packet_count gpr_b_rel 00
*l0000!sopbit gpr_b_rel 0E
*l0000!eopbit gpr_a_rel 03
*l0000!bytecnt gpr_b_rel 03
*l0000!elem gpr_a_rel 04
*l0000!rx_channel_num gpr_b_rel 04
;*l0000!rxconfigdata!!2 gpr_b_rel 05
*l0000!rxconfigdata gpr_b_rel 05
*l0000!rbuf gpr_b_rel 06
*l0000!sramdescbase gpr_a_rel 05
*l0000!drampacketbase gpr_a_rel 06
*$l0000!sr0 sram_rel 00 0 both 4 0x33
*$l0000!sr1 sram_rel 01 0 both 3 0x33
*$l0000!sr2 sram_rel 02 0 both 2 0x33
*$l0000!sr3 sram_rel 03 0 both 1 0x33
*l0001!temp gpr_b_rel 00
*l0002!channel_number gpr_b_rel 06
;*l0003!rxthreadlist!!2 gpr_b_rel 0F
;*l0003!rxthreadlist!!3 gpr_b_rel 0F
*l0003!rxthreadlist gpr_b_rel 0F
*l0004!rxconfigdata0 gpr_b_rel 0D
*$l0004!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0004!msfaddress gpr_b_rel 0E
*l0005!temp_reg gpr_b_rel 0F
*l0005!temp gpr_b_rel 03
*l0006!rxupcontrol0 gpr_b_rel 04
*$l0006!rxconfigdata0 sram_rel 00 0 both 1 0x0
;*l0006!msfaddress!!2 gpr_b_rel 07
;*l0006!msfaddress!!3 gpr_b_rel 07
;*l0006!msfaddress!!4 gpr_b_rel 07
*l0006!msfaddress gpr_b_rel 07
*l0007!rxconfigdata0 gpr_b_rel 08
*$l0007!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0007!msfaddress gpr_b_rel 09
*l0008!cellcount gpr_b_rel 07
*l0008!freelist gpr_b_rel 08
*$l0008!s0 sram_rel 00 0 both 3 0x15
*$l0008!s1 sram_rel 01 0 both 2 0x15
*$l0008!s2 sram_rel 02 0 both 1 0x15
;*l0008!tmp!!2 gpr_b_rel 09
;*l0008!tmp!!3 gpr_b_rel 09
;*l0008!tmp!!4 gpr_b_rel 09
*l0008!tmp gpr_b_rel 09
*l0009!pci_base gpr_a_rel 0A
*l0009!pci_offset gpr_b_rel 0C
*l0009!temp gpr_b_rel 0D
*$l0009!pci_rw sram_rel 00 0 both 1 0x0
;*l0010!cur_rbuf_addr!!2 gpr_b_rel 0A
;*l0010!cur_rbuf_addr!!3 gpr_a_rel 07
*l0010!cur_rbuf_addr gpr_b_rel 0A
;*l0010!refcnt!!2 gpr_b_rel 0B
;*l0010!refcnt!!3 gpr_b_rel 0B
*l0010!refcnt gpr_b_rel 0B
*l0010!rel gpr_b_rel 01
*l0010!freebuffer gpr_b_rel 02
*l0011!temp gpr_b_rel 0C
*l0012!temp gpr_a_rel 0B
*l0010!sig_free_buf signal 01 0
*l0009!pci_sig signal 01 0
*l0008!qa_init signal 01 0
*l0008!qa_init!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig signal 01 0
*l0000!dram_sig signal 02 0
*l0000!scratch_sig signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var l0012!temp 0 R
.%liverange 0 A11 132:135
.%liverange 0 ~A11 96:131 136:136
.%var l0011!temp 0 R
.%liverange 0 B12 126:136
.%liverange 0 ~B12 96:125
.%var l0010!freebuffer 0 R
.%liverange 0 B2 107:107
.%var l0010!rel 0 R
.%liverange 0 B1 109:109
.%var l0010!refcnt 0 R
.%liverange 0 B11 114:136
.%liverange 0 ~B11 96:113
.%var l0010!cur_rbuf_addr 0 R
.%liverange 0 B10 111:112
.%liverange 0 A7 113:136
.%liverange 0 ~A7 96:110
.%var $l0009!pci_rw 0 R
.%liverange 0 $W0 92:95
.%liverange 0 ~$W0 96:132 136:136
.%liverange 0 $R0 137:137
.%var l0009!temp 0 R
.%liverange 0 B13 91:95
.%liverange 0 ~B13 96:136
.%var l0009!pci_offset 0 R
.%liverange 0 B12 90:95
.%liverange 0 ~B12 96:125
.%var l0009!pci_base 0 R
.%liverange 0 A10 88:95
.%liverange 0 ~A10 96:136
.%var l0008!tmp 0 R
.%liverange 0 B9 71:95
.%liverange 0 ~B9 96:136
.%var $l0008!s2 0 R
.%liverange 0 $W2 75:95
.%liverange 0 ~$W2 96:136
.%liverange 0 $R2 137:137
.%var $l0008!s1 0 R
.%liverange 0 $W1 74:95
.%liverange 0 ~$W1 96:136
.%liverange 0 $R1 137:137
.%var $l0008!s0 0 R
.%liverange 0 $W0 73:91
.%liverange 0 $R0 137:137
.%var l0008!freelist 0 R
.%liverange 0 B8 81:95
.%liverange 0 ~B8 96:136
.%var l0008!cellcount 0 R
.%liverange 0 B7 82:95
.%liverange 0 ~B7 96:136
.%var l0007!msfaddress 0 R
.%liverange 0 B9 66:70
.%var $l0007!rxconfigdata0 0 R
.%liverange 0 $W0 69:72
.%liverange 0 $R0 137:137
.%var l0007!rxconfigdata0 0 R
.%liverange 0 B8 67:80
.%var l0006!msfaddress 0 R
.%liverange 0 B7 54:81
.%var $l0006!rxconfigdata0 0 R
.%liverange 0 $W0 55:68
.%liverange 0 $R0 137:137
.%var l0006!rxupcontrol0 0 R
.%liverange 0 B4 53:95
.%liverange 0 ~B4 96:102
.%var l0005!temp 0 R
.%liverange 0 B3 48:95
.%liverange 0 ~B3 47:47 96:101
.%var l0005!temp_reg 0 R
.%liverange 0 B15 47:95
.%liverange 0 ~B15 96:136
.%var l0004!msfaddress 0 R
.%liverange 0 B14 42:95
.%liverange 0 ~B14 96:99
.%var $l0004!rxconfigdata0 0 R
.%liverange 0 $W0 45:54
.%liverange 0 $R0 137:137
.%var l0004!rxconfigdata0 0 R
.%liverange 0 B13 43:90
.%var l0003!rxthreadlist 0 R
.%liverange 0 B15 23:46
.%liverange 0 ~B15 96:136
.%var l0002!channel_number 0 R
.%liverange 0 B6 16:21
.%var l0001!temp 0 R
.%liverange 0 B0 8:10
.%var $l0000!sr3 0 R
.%liverange 0 $W3 137:137
.%liverange 0 $R3 137:137
.%var $l0000!sr2 0 R
.%liverange 0 $W2 137:137
.%liverange 0 $R2 137:137
.%var $l0000!sr1 0 R
.%liverange 0 $W1 137:137
.%liverange 0 $R1 137:137
.%var $l0000!sr0 0 R
.%liverange 0 $W0 137:137
.%liverange 0 $R0 79:95 106:109
.%liverange 0 ~$R0 96:105 110:136
.%var l0000!drampacketbase 0 R
.%liverange 0 A6 18:136
.%var l0000!sramdescbase 0 R
.%liverange 0 A5 20:136
.%var l0000!rbuf 0 R
.%liverange 0 B6 22:136
.%var l0000!rxconfigdata 0 R
.%liverange 0 B5 26:136
.%var l0000!rx_channel_num 0 R
.%liverange 0 B4 103:136
.%liverange 0 ~B4 96:102
.%var l0000!elem 0 R
.%liverange 0 A4 99:136
.%liverange 0 ~A4 96:98
.%var l0000!bytecnt 0 R
.%liverange 0 B3 102:136
.%liverange 0 ~B3 96:101
.%var l0000!eopbit 0 R
.%liverange 0 A3 101:136
.%liverange 0 ~A3 96:100
.%var l0000!sopbit 0 R
.%liverange 0 B14 100:136
.%liverange 0 ~B14 96:99
.%var l0000!packet_count 0 R
.%liverange 0 B0 11:14
.%var l0000!t0 0 R
.%liverange 0 A2 17:136
.%var $l0000!scratch_data 0 R
.%liverange 0 $W0 133:135
.%liverange 0 ~$W0 96:132 136:136
.%liverange 0 $R0 137:137
.%var $l0000!transferreg01 0 R
.%liverange 0 $W2 137:137
.%liverange 0 $R2 137:137
.%var $l0000!transferreg00 0 R
.%liverange 0 $W1 0:73
.%liverange 0 ~$W1 96:136
.%liverange 0 $R1 0:136
.%var l0000!bdptr 0 R
.%liverange 0 B2 14:106 108:136
.%var l0000!pkt_buff_addr 0 R
.%liverange 0 B1 13:108 110:136
.%var l0000!packet_size 0 R
.%liverange 0 A1 12:136
.%var l0000!ring_num 0 R
.%liverange 0 B0 15:136
.%var l0000!threadfreelist_addr 0 R
.%liverange 0 A0 30:30 34:34 38:38 40:136
.%var l0000!cur_ctx 0 R
.%liverange 0 A9 10:136
.%var l0000!cur_me 0 R
.%liverange 0 A8 9:136
.%var l0010!sig_free_buf 1 R
.%liverange 0 G1 106:106
.%var l0009!pci_sig 1 R
.%liverange 0 G1 93:93
.%var l0008!qa_init 1 R
.%liverange 0 G1 76:76 79:79
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:1
.%var l0000!rx_sig 1 R
.%liverange 0 G1 96:98
.%var l0000!dram_sig 1 R
.%liverange 0 D2 124:125
.%var l0000!scratch_sig 1 R
.%liverange 0 G1 135:135
.%var l0000!msf_sig 1 R
.%liverange 0 G1 46:46 56:56 59:59 62:62 65:65 70:70
.%scope end
.0 E000008000 common_code
	.import_var __chip_id __chip_revision __uengine_id
	.%line 61 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bw\sys_loopback_bw_in_rx.uc" 1 0
	.reg l0000!cur_me l0000!cur_ctx l0000!threadfreelist_addr
	.%line 62 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bw\sys_loopback_bw_in_rx.uc" 1 0
	.reg l0000!ring_num l0000!packet_size l0000!pkt_buff_addr l0000!bdptr
	.%line 63 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bw\sys_loopback_bw_in_rx.uc" 1 0
	.reg $l0000!transferreg00 $l0000!transferreg01 $l0000!scratch_data