sys_loopback_bw_eg_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.0.411
+uca_date: Sep  9 2002 00:25:20
+current_date: Tue Oct 29 18:44:34 2002

.cpu_version 0x00000002 0 15

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:cont1# 93
:context_enable_csr_config# 67
:fill# 109
:init_rbuf# 25
:init_value# 2
:l000_01# 86
:l000_end# 86
:l001_01# 96
:l001_end# 96
:l002_01# 107
:l002_end# 107
:l003_01# 116
:l003_end# 116
:next_packet# 116
:receivepacket# 73
:rsw# 75
*-- no_destination 0
*l0000!temp gpr_b_rel 0E
*l0000!sopbit gpr_b_rel 09
*l0000!eopbit gpr_b_rel 00
*l0000!port_num gpr_b_rel 01
*l0000!rxthreadlist gpr_b_rel 01
;*l0000!bytecnt!!2 gpr_b_rel 02
*l0000!bytecnt gpr_b_rel 02
*l0000!elem gpr_a_rel 00
*l0000!packet_count gpr_b_rel 03
*l0000!ring_num gpr_a_rel 01
*l0000!packet_num gpr_a_rel 02
*l0000!packet_size gpr_a_rel 03
*l0000!pkt_buff_addr gpr_b_rel 03
;*l0000!rxconfigdata0!!2 gpr_b_rel 0A
*l0000!rxconfigdata0 gpr_b_rel 0A
*l0000!rbuf gpr_b_rel 04
;*l0000!msfaddress!!2 gpr_b_rel 0B
;*l0000!msfaddress!!3 gpr_b_rel 0B
*l0000!msfaddress gpr_b_rel 0B
*l0000!msfaddress0 gpr_a_rel 04
*l0000!msfaddress1 gpr_a_rel 05
*$l0000!temp0 sram_rel 00 0 both 1 0x0
*$l0000!temp1 sram_rel 00 0 both 1 0x0
*$l0000!scratch_data sram_rel 00 0 both 1 0x0
*$l0000!transferreg00 sram_rel 00 0 both 2 0x1D
*$l0000!transferreg01 sram_rel 01 0 both 1 0x1D
;*l0000!rxconfigdata!!2 gpr_b_rel 05
*l0000!rxconfigdata gpr_b_rel 05
*$l0000!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0000!scratch_addr gpr_b_rel 04
*l0000!drampacketbase gpr_b_rel 06
*$l0000!prepend_data0 sram_rel 01 0 both 2 0x13
*$l0000!prepend_data1 sram_rel 02 0 both 1 0x13
*l0001!temp_reg gpr_b_rel 0C
*l0001!temp gpr_b_rel 0D
*$l0002!scratch_base sram_rel 00 0 both 1 0x0
*$l0002!scratch_head sram_rel 01 0 both 1 0x0
*$l0002!scratch_tail sram_rel 02 0 both 1 0x0
*l0003!ctxenabledata gpr_b_rel 0F
;*l0004!cur_rbuf_addr!!2 gpr_b_rel 07
;*l0004!cur_rbuf_addr!!3 gpr_b_rel 07
;*l0004!cur_rbuf_addr!!4 gpr_a_rel 06
*l0004!cur_rbuf_addr gpr_b_rel 07
;*l0004!refcnt!!2 gpr_b_rel 08
;*l0004!refcnt!!3 gpr_b_rel 08
*l0004!refcnt gpr_b_rel 08
*l0005!temp gpr_b_rel 00
*l0002!scratch_sig3 signal 03 0
*l0002!scratch_sig3!!6 signal 03 0
*l0002!scratch_sig3!!5 signal 03 0
*l0002!scratch_sig3!!4 signal 03 0
*l0002!scratch_sig3!!3 signal 03 0
*l0002!scratch_sig3!!2 signal 03 0
*l0002!scratch_sig2 signal 02 0
*l0002!scratch_sig2!!6 signal 02 0
*l0002!scratch_sig2!!5 signal 02 0
*l0002!scratch_sig2!!4 signal 02 0
*l0002!scratch_sig2!!3 signal 02 0
*l0002!scratch_sig2!!2 signal 02 0
*l0002!scratch_sig1 signal 01 0
*l0002!scratch_sig1!!6 signal 01 0
*l0002!scratch_sig1!!5 signal 01 0
*l0002!scratch_sig1!!4 signal 01 0
*l0002!scratch_sig1!!3 signal 01 0
*l0002!scratch_sig1!!2 signal 01 0
*l0000!scratch_sig signal 01 0
*l0000!sig_dram_xfer1 signal 02 0
*l0000!rx_sig signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var l0005!temp 0 R
.%liverange 0 B0 108:115
.%liverange 0 ~B0 73:81 116:116
.%var l0004!refcnt 0 R
.%liverange 0 B8 90:116
.%liverange 0 ~B8 73:89
.%var l0004!cur_rbuf_addr 0 R
.%liverange 0 B7 79:88
.%liverange 0 A6 89:116
.%liverange 0 ~A6 73:78
.%var l0003!ctxenabledata 0 R
.%liverange 0 B15 68:116
.%var $l0002!scratch_tail 0 R
.%liverange 0 $W2 37:116
.%liverange 0 $R2 117:117
.%var $l0002!scratch_head 0 R
.%liverange 0 $W1 36:116
.%liverange 0 $R1 117:117
.%var $l0002!scratch_base 0 R
.%liverange 0 $W0 38:72
.%liverange 0 ~$W0 73:101
.%liverange 0 $R0 117:117
.%var l0001!temp 0 R
.%liverange 0 B13 26:116
.%liverange 0 ~B13 25:25
.%var l0001!temp_reg 0 R
.%liverange 0 B12 25:116
.%var $l0000!prepend_data1 0 R
.%liverange 0 $W2 117:117
.%liverange 0 $R2 80:116
.%liverange 0 ~$R2 73:79
.%var $l0000!prepend_data0 0 R
.%liverange 0 $W1 117:117
.%liverange 0 $R1 80:116
.%liverange 0 ~$R1 73:79
.%var l0000!drampacketbase 0 R
.%liverange 0 B6 9:116
.%var l0000!scratch_addr 0 R
.%liverange 0 B4 7:12
.%var $l0000!rxconfigdata0 0 R
.%liverange 0 $W0 19:22 34:37
.%liverange 0 $R0 117:117
.%var l0000!rxconfigdata 0 R
.%liverange 0 B5 15:116
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 0:35
.%liverange 0 $R1 0:72
.%liverange 0 ~$R1 73:79
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:18
.%liverange 0 $R0 0:116
.%var $l0000!scratch_data 0 R
.%liverange 0 $W0 109:115
.%liverange 0 ~$W0 73:101 116:116
.%liverange 0 $R0 117:117
.%var $l0000!temp1 0 R
.%liverange 0 $W0 23:33
.%liverange 0 $R0 117:117
.%var $l0000!temp0 0 R
.%liverange 0 $W0 102:108
.%liverange 0 ~$W0 73:101 116:116
.%liverange 0 $R0 117:117
.%var l0000!msfaddress1 0 R
.%liverange 0 A5 12:116
.%var l0000!msfaddress0 0 R
.%liverange 0 A4 11:116
.%var l0000!msfaddress 0 R
.%liverange 0 B11 20:116
.%var l0000!rbuf 0 R
.%liverange 0 B4 13:116
.%var l0000!rxconfigdata0 0 R
.%liverange 0 B10 17:116
.%var l0000!pkt_buff_addr 0 R
.%liverange 0 B3 6:116
.%var l0000!packet_size 0 R
.%liverange 0 A3 5:116
.%var l0000!packet_num 0 R
.%liverange 0 A2 4:116
.%var l0000!ring_num 0 R
.%liverange 0 A1 8:116
.%var l0000!packet_count 0 R
.%liverange 0 B3 3:5
.%var l0000!elem 0 R
.%liverange 0 A0 76:116
.%liverange 0 ~A0 73:75
.%var l0000!bytecnt 0 R
.%liverange 0 B2 77:116
.%liverange 0 ~B2 73:76
.%var l0000!rxthreadlist 0 R
.%liverange 0 B1 14:72
.%liverange 0 ~B1 73:82
.%var l0000!port_num 0 R
.%liverange 0 B1 83:116
.%liverange 0 ~B1 73:82
.%var l0000!eopbit 0 R
.%liverange 0 B0 82:107
.%liverange 0 ~B0 73:81 116:116
.%var l0000!sopbit 0 R
.%liverange 0 B9 81:116
.%liverange 0 ~B9 73:80
.%var l0000!temp 0 R
.%liverange 0 B14 71:116
.%var l0002!scratch_sig3 1 R
.%liverange 0 G3 41:42
.%liverange 0 G3 46:47 51:52 56:57 61:62 66:67
.%var l0002!scratch_sig2 1 R
.%liverange 0 G2 40:42 45:47 50:52 55:57 60:62 65:67
.%var l0002!scratch_sig1 1 R
.%liverange 0 G1 39:42 44:47 49:52 54:57 59:62 64:67
.%var l0000!scratch_sig 1 R
.%liverange 0 G1 111:111
.%var l0000!sig_dram_xfer1 1 R
.%liverange 0 D2 100:101
.%var l0000!rx_sig 1 R
.%liverange 0 G1 73:75
.%var l0000!msf_sig 1 R
.%liverange 0 G1 21:21 24:24 35:35 80:80 103:103
.%scope end
.0 D800800010 common_code
	.import_var __chip_id __chip_revision __uengine_id
	.%line 64 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bw\sys_loopback_bw_eg_rx.uc" 1 0
	.reg l0000!tmp0 l0000!tmp1 l0000!temp
	.%line 65 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bw\sys_loopback_bw_eg_rx.uc" 1 0
	.reg l0000!sopbit l0000!eopbit l0000!port_num
	.%line 66 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bw\sys_loopback_bw_eg_rx.uc" 1 0
	.reg l0000!rxthreadlist
	.%line 67 "C:\Angel-Island\diag\test_suites\microcode\sys_loopback_bw\sys_loopback_bw_eg_rx.uc" 1 0