sf_loopback_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 11:53:11 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:context_enable_csr_config# 1
:end# 51
:init_rbuf# 10
:init_value# 0
:receivepacket# 32
:rsw# 34
*-- no_destination 0
*l0000!tmp0 gpr_b_rel 06
*l0000!rxthreadlist gpr_b_rel 02
*l0000!bytecnt gpr_b_rel 07
*l0000!elem gpr_a_rel 00
;*l0000!rxconfigdata0!!2 gpr_b_rel 08
*l0000!rxconfigdata0 gpr_b_rel 08
*l0000!rbuf gpr_a_rel 01
*l0000!rbuf_offset gpr_b_rel 03
;*l0000!msfaddress!!2 gpr_b_rel 09
;*l0000!msfaddress!!3 gpr_b_rel 09
;*l0000!msfaddress!!4 gpr_b_rel 09
*l0000!msfaddress gpr_b_rel 09
*l0000!msfaddress0 gpr_b_rel 04
*l0000!msfaddress1 gpr_b_rel 00
*$l0000!temp0 sram_rel 00 0 both 1 0x0
*$l0000!temp1 sram_rel 00 0 both 1 0x0
*$l0000!transferreg00 sram_rel 00 0 both 2 0xF
*$l0000!transferreg01 sram_rel 01 0 both 1 0xF
*$l0000!rxconfigdata sram_rel 00 0 both 1 0x0
*$l0000!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0001!ctxenabledata gpr_b_rel 0A
*l0002!temp_reg gpr_b_rel 0B
*l0002!temp gpr_b_rel 0C
*l0003!temp gpr_b_rel 05
*l0003!drampacketbase gpr_b_rel 01
*$l0004!pci_rw sram_rel 00 0 both 1 0x0
*l0004!pci_base gpr_a_rel 02
*l0004!pci_offset gpr_b_rel 0D
*l0004!pci_sig signal 01 0
*l0000!sig_dram_xfer1 signal 02 0
*l0000!sig_thd signal 02 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var l0004!pci_offset 0 R
.%liverange 0 B13 50:50
.%liverange 0 ~B13 51:51
.%var l0004!pci_base 0 R
.%liverange 0 A2 48:50
.%liverange 0 ~A2 51:51
.%var $l0004!pci_rw 0 R
.%liverange 0 $W0 47:50
.%liverange 0 ~$W0 51:51
.%liverange 0 $R0 52:52
.%var l0003!drampacketbase 0 R
.%liverange 0 B1 37:50
.%liverange 0 ~B1 51:51
.%var l0003!temp 0 R
.%liverange 0 B5 40:50
.%liverange 0 ~B5 51:51
.%var l0002!temp 0 R
.%liverange 0 B12 11:50
.%liverange 0 ~B12 10:10 51:51
.%var l0002!temp_reg 0 R
.%liverange 0 B11 10:50
.%liverange 0 ~B11 51:51
.%var l0001!ctxenabledata 0 R
.%liverange 0 B10 2:50
.%liverange 0 ~B10 51:51
.%var $l0000!rxconfigdata0 0 R
.%liverange 0 $W0 8:16 26:31
.%liverange 0 $R0 52:52
.%var $l0000!rxconfigdata 0 R
.%liverange 0 $W0 32:43
.%liverange 0 $R0 52:52
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 0:51
.%liverange 0 $R1 0:51
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:7
.%liverange 0 ~$W0 51:51
.%liverange 0 $R0 0:51
.%var $l0000!temp1 0 R
.%liverange 0 $W0 17:25
.%liverange 0 $R0 52:52
.%var $l0000!temp0 0 R
.%liverange 0 $W0 44:46
.%liverange 0 $R0 52:52
.%var l0000!msfaddress1 0 R
.%liverange 0 B0 29:50
.%liverange 0 ~B0 51:51
.%var l0000!msfaddress0 0 R
.%liverange 0 B4 28:50
.%liverange 0 ~B4 51:51
.%var l0000!msfaddress 0 R
.%liverange 0 B9 5:50
.%liverange 0 ~B9 51:51
.%var l0000!rbuf_offset 0 R
.%liverange 0 B3 39:50
.%liverange 0 ~B3 51:51
.%var l0000!rbuf 0 R
.%liverange 0 A1 30:50
.%liverange 0 ~A1 51:51
.%var l0000!rxconfigdata0 0 R
.%liverange 0 B8 6:50
.%liverange 0 ~B8 51:51
.%var l0000!elem 0 R
.%liverange 0 A0 35:50
.%liverange 0 ~A0 51:51
.%var l0000!bytecnt 0 R
.%liverange 0 B7 36:50
.%liverange 0 ~B7 51:51
.%var l0000!rxthreadlist 0 R
.%liverange 0 B2 31:50
.%liverange 0 ~B2 51:51
.%var l0000!tmp0 0 R
.%liverange 0 B6 16:50
.%liverange 0 ~B6 51:51
.%var l0004!pci_sig 1 R
.%liverange 0 G1 51:51
.%var l0000!sig_dram_xfer1 1 R
.%liverange 0 D2 42:43
.%var l0000!sig_thd 1 R
.%liverange 0 G2 0:34
.%var l0000!msf_sig 1 R
.%liverange 0 G1 9:9 19:19 22:22 27:27 33:34 45:46
.%scope end
.0 D80CC00011 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 54 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.reg l0000!tmp0
	.%line 55 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.reg l0000!rxthreadlist
	.%line 56 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.reg l0000!bytecnt l0000!elem
	.%line 57 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.reg l0000!rxconfigdata0
	.%line 58 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.reg l0000!rbuf l0000!rbuf_offset
	.%line 59 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.reg l0000!msfaddress l0000!msfaddress0 l0000!msfaddress1
	.%line 60 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.reg $l0000!temp0 $l0000!temp1
	.%line 61 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.reg $l0000!transferreg00 $l0000!transferreg01
	.%line 62 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.reg $l0000!rxconfigdata $l0000!rxconfigdata0
	.%line 64 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.sig l0000!msf_sig l0000!scratch1 l0000!sig_thd l0000!sig_dram_xfer1
	.%line 65 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.xfer_order $l0000!transferreg00 $l0000!transferreg01
	.%line 67 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.set_sig l0000!sig_thd
	.%line 68 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.set $l0000!transferreg00 $l0000!transferreg01
	.%line 71 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0 51
	init_value#:
	.%line 72 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0 51
		br!=ctx[0, end#]
.1 F000102B00 common_code
	.%line 108 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	.local l0001!ctxenabledata
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
	context_enable_csr_config#:
	.%line 109 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
		immed[l0001!ctxenabledata, 256]
.2 F440002B10 common_code
	.%line 110 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0
		immed_w1[l0001!ctxenabledata, 16]
.3 FC01A02B00 common_code
	.%line 111 "C:\phase9rel\diag\test_suites\microcode\sf_loopback\sf_loopback_rx.uc" 1 0