sys_loopback_bw_3_eg_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:01:26 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:cont_comp_tbuf_tx_sequnce# 85
:init# 2
:init_msf# 36
:l000_01# 20
:l000_02# 25
:l000_03# 30
:l000_end# 32
:l001_01# 115
:l001_end# 116
:l002_01# 106
:l002_end# 106
:msf_init_done# 65
:next_burst# 66
:next_packet# 74
:read_tx_sequence_loop# 78
:wait_for_xscale# 110
*-- no_destination 0
*l0000!cur_me gpr_b_rel 04
;*l0000!msfaddress!!2 gpr_b_rel 05
;*l0000!msfaddress!!3 gpr_b_rel 05
;*l0000!msfaddress!!4 gpr_b_rel 05
;*l0000!msfaddress!!5 gpr_b_rel 05
;*l0000!msfaddress!!6 gpr_b_rel 05
;*l0000!msfaddress!!7 gpr_a_rel 05
;*l0000!msfaddress!!8 gpr_a_rel 05
*l0000!msfaddress gpr_b_rel 05
*l0000!txsequenceaddr gpr_b_rel 00
*l0000!pkt_in_one_burst gpr_a_rel 00
*l0000!pkt_in_cur_burst gpr_b_rel 06
*l0000!total_loop gpr_a_rel 01
*l0000!cur_loop gpr_b_rel 01
;*l0000!future_count_value!!2 gpr_b_rel 07
*l0000!future_count_value gpr_a_rel 02
*l0000!future_count_incr gpr_b_rel 02
*l0000!byte_count gpr_a_rel 03
*$l0000!misc_ctrl_val sram_rel 00 0 both 1 0x0
;*l0000!txconfigdata0!!2 gpr_b_rel 08
;*l0000!txconfigdata0!!3 gpr_b_rel 08
*l0000!txconfigdata0 gpr_b_rel 08
*$l0000!txconfigdata0 sram_rel 00 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x1D
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x1D
;*l0000!tbuf_element!!2 gpr_b_rel 09
*l0000!tbuf_element gpr_a_rel 04
*l0000!base_element_for_port gpr_b_rel 03
*l0001!temp gpr_b_rel 01
*l0002!temp_scratch_addr gpr_b_rel 00
*$l0002!temp_scratch_data sram_rel 00 0 both 1 0x0
*l0003!temp_scratch_addr gpr_b_rel 03
*$l0003!temp_scratch_data sram_rel 00 0 both 1 0x0
;*l0004!temp!!2 gpr_b_rel 0F
;*l0004!temp!!3 gpr_b_rel 0F
*l0004!temp gpr_b_rel 0F
;*l0005!result!!2 gpr_b_rel 0A
*l0005!result gpr_a_rel 06
*l0005!tmp_val gpr_b_rel 0B
*l0005!tmp_tbuf gpr_b_rel 0C
*$l0005!txsequencedata sram_rel 01 0 both 1 0x0
*l0006!temp gpr_b_rel 0D
*l0006!cur_tbuf_elem gpr_b_rel 0E
*$l0007!temp_reg_val sram_rel 02 0 both 1 0x0
;*l0007!temp_scratch_addr!!2 gpr_b_rel 06
*l0007!temp_scratch_addr gpr_a_rel 07
*$l0007!temp_scratch_data sram_rel 01 0 both 1 0x0
*l0007!scratch_sig signal 02 0
*l0003!scratch_sig signal 01 0
*l0002!scratch_sig signal 01 0
*l0000!cap_sig signal 02 0
*l0000!cap_sig!!2 signal 02 0
*l0000!inter_me_sig signal 0F 0
*l0000!future_count_sig signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!8 signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var $l0007!temp_scratch_data 0 R
.%liverange 0 $W1 110:114
.%liverange 0 ~$W1 66:93
.%liverange 0 $R1 111:114
.%liverange 0 ~$R1 66:78 110:110
.%var l0007!temp_scratch_addr 0 R
.%liverange 0 A7 108:108
.%liverange 0 B6 109:114
.%liverange 0 ~B6 66:66
.%var $l0007!temp_reg_val 0 R
.%liverange 0 $W2 102:114
.%liverange 0 ~$W2 66:101 115:116
.%liverange 0 $R2 117:117
.%var l0006!cur_tbuf_elem 0 R
.%liverange 0 B14 89:116
.%liverange 0 ~B14 66:88
.%var l0006!temp 0 R
.%liverange 0 B13 92:116
.%liverange 0 ~B13 66:91
.%var $l0005!txsequencedata 0 R
.%liverange 0 $W1 117:117
.%liverange 0 $R1 79:109 115:116
.%liverange 0 ~$R1 74:78 110:110
.%var l0005!tmp_tbuf 0 R
.%liverange 0 B12 84:116
.%liverange 0 ~B12 66:83
.%var l0005!tmp_val 0 R
.%liverange 0 B11 81:116
.%liverange 0 ~B11 66:80
.%var l0005!result 0 R
.%liverange 0 A6 80:85
.%liverange 0 B10 86:116
.%liverange 0 ~B10 66:79
.%var l0004!temp 0 R
.%liverange 0 B15 57:64
.%liverange 0 ~B15 65:116
.%var $l0003!temp_scratch_data 0 R
.%liverange 0 $W0 117:117
.%liverange 0 $R0 14:65
.%var l0003!temp_scratch_addr 0 R
.%liverange 0 B3 13:17 20:22 25:27 30:30
.%var $l0002!temp_scratch_data 0 R
.%liverange 0 $W0 117:117
.%liverange 0 $R0 11:13
.%var l0002!temp_scratch_addr 0 R
.%liverange 0 B0 10:18 20:23 25:28 30:31
.%var l0001!temp 0 R
.%liverange 0 B1 4:7
.%var l0000!base_element_for_port 0 R
.%liverange 0 B3 18:19 23:24 28:29 31:116
.%var l0000!tbuf_element 0 R
.%liverange 0 A4 6:96 98:116
.%liverange 0 B9 97:97
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 94:109 115:116
.%liverange 0 ~$W1 74:93
.%liverange 0 $R1 117:117
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 93:116
.%liverange 0 ~$W0 66:92
.%liverange 0 $R0 117:117
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W0 40:64
.%liverange 0 ~$W0 65:92
.%liverange 0 $R0 117:117
.%var l0000!txconfigdata0 0 R
.%liverange 0 B8 38:64
.%liverange 0 ~B8 65:116
.%var $l0000!misc_ctrl_val 0 R
.%liverange 0 $W0 117:117
.%liverange 0 $R0 66:116
.%var l0000!byte_count 0 R
.%liverange 0 A3 7:116
.%var l0000!future_count_incr 0 R
.%liverange 0 B2 9:116
.%var l0000!future_count_value 0 R
.%liverange 0 A2 68:75 77:116
.%liverange 0 ~A2 66:67
.%liverange 0 B7 76:76
.%var l0000!cur_loop 0 R
.%liverange 0 B1 8:116
.%var l0000!total_loop 0 R
.%liverange 0 A1 12:116
.%var l0000!pkt_in_cur_burst 0 R
.%liverange 0 B6 67:108 115:116
.%var l0000!pkt_in_one_burst 0 R
.%liverange 0 A0 15:116
.%var l0000!txsequenceaddr 0 R
.%liverange 0 B0 19:19 24:24 29:29 32:116
.%var l0000!msfaddress 0 R
.%liverange 0 B5 37:64
.%liverange 0 ~B5 65:89
.%liverange 0 A5 90:116
.%liverange 0 ~A5 66:89
.%var l0000!cur_me 0 R
.%liverange 0 B4 5:116
.%var l0007!scratch_sig 1 R
.%liverange 0 D2 111:112
.%var l0003!scratch_sig 1 R
.%liverange 0 G1 14:14
.%var l0002!scratch_sig 1 R
.%liverange 0 G1 11:11
.%var l0000!cap_sig 1 R
.%liverange 0 G2 66:66 103:107
.%var l0000!inter_me_sig 1 R
.%liverange 0 G15 0:0 2:35
.%var l0000!future_count_sig 1 R
.%liverange 0 G1 88:95
.%var l0000!msf_sig 1 R
.%liverange 0 G1 41:41 45:45 47:47 49:49 51:51 56:56 79:79 96:107 115:116
.%scope end
.0 D800800010 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 81 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg l0000!cur_me
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg l0000!msfaddress l0000!txsequenceaddr
	.%line 83 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg l0000!pkt_in_one_burst l0000!pkt_in_cur_burst
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg l0000!total_loop l0000!cur_loop
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg l0000!future_count_value l0000!future_count_incr
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg l0000!byte_count
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg $l0000!misc_ctrl_val
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg l0000!txconfigdata0
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg $l0000!txconfigdata0
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 91 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.reg l0000!tbuf_element l0000!base_element_for_port
	.%line 92 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.sig l0000!msf_sig l0000!future_count_sig l0000!inter_me_sig l0000!cap_sig
	.%line 94 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_3\sys_loopback_bw_3_eg_tx.uc" 1 0
	.xfer_order $l0000!txcontrolword0 $l0000!txcontrolword1