me_timers_counters_test.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* ME_Timers_Counters_Test.uc
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXP2400
 *  subsystem: DIAG
 *  author: ccm, Mar 25, 02
 * 
 * --------------------------------------------------------------------------
 */
#include "../../../include/me_xscale_sync.h"

#macro multi_nop(loops)
#define X 0
#while(X < loops)
nop
#define_eval X (X + 1)
#endloop
#undef X
#endm

#define CTX_TO_BE_TESTED 0

#define ME1_INTER_THREAD_SIG1 ((1<<7) + 1 + (CTX_TO_BE_TESTED<<4))
#define ME2_INTER_THREAD_SIG1 ((2<<7) + 1 + (CTX_TO_BE_TESTED<<4))
#define ME3_INTER_THREAD_SIG1 ((3<<7) + 1 + (CTX_TO_BE_TESTED<<4))
#define ME4_INTER_THREAD_SIG1 ((16<<7) + 1 + (CTX_TO_BE_TESTED<<4))
#define ME5_INTER_THREAD_SIG1 ((17<<7) + 1 + (CTX_TO_BE_TESTED<<4))
#define ME6_INTER_THREAD_SIG1 ((18<<7) + 1 + (CTX_TO_BE_TESTED<<4))
#define ME7_INTER_THREAD_SIG1 ((19<<7) + 1 + (CTX_TO_BE_TESTED<<4))

br!=ctx[CTX_TO_BE_TESTED, END#]	// only one ctx in each ME is required for the test

#define SIGNAL1 0x1
#define SIGNAL2 0x2

.reg scratch_base timer_wr_low timer_rd_low me_offset me
.sig scratch_write signal_1 signal_2
.addr signal_1 SIGNAL1
.addr signal_2 SIGNAL2
.reg $status0

ctx_arb[voluntary]
// initialization
immed[scratch_base, 0]
immed[timer_rd_low, 0]
immed[timer_wr_low, 0]

// calculate me_offset
local_csr_rd[active_ctx_sts]
immed[me, 0]
alu_shf[me, 0x1f, AND, me, >>3]
alu[me_offset, 0x3, AND, me]
alu[--, me, -, 0x3]
ble[me_offset_obtain#]

alu[me_offset, me_offset, OR, 0x4]

me_offset_obtain#:
alu_shf[me_offset, --, B, me_offset, <<2]

alu[--, me, -, 0x0]	// if ME0
bne[me1_me7#]
	cap[fast_wr, 0x100, MISC_CONTROL]	// ME0 disables TIMERSTAMP_EN
	multi_nop(3)
	// ME0 inter-threads ME1-ME7
	cap[fast_wr, ME1_INTER_THREAD_SIG1, interthread_sig]
	cap[fast_wr, ME2_INTER_THREAD_SIG1, interthread_sig]
	cap[fast_wr, ME3_INTER_THREAD_SIG1, interthread_sig]
	cap[fast_wr, ME4_INTER_THREAD_SIG1, interthread_sig]
	cap[fast_wr, ME5_INTER_THREAD_SIG1, interthread_sig]
	cap[fast_wr, ME6_INTER_THREAD_SIG1, interthread_sig]
	cap[fast_wr, ME7_INTER_THREAD_SIG1, interthread_sig]
	br[timestamp_disabled#]

me1_me7#:
	ctx_arb[signal_1] // ME1-ME7 waits for ME0 to signal

timestamp_disabled#:
// TIMESTAMP has been disabled and the timestamp can now be set
immed_w0[timer_wr_low,0xFFFF]
immed_w1[timer_wr_low,0xFFFF]
local_csr_wr[Timestamp_low, timer_wr_low]

// Counter for timestamp to be trigerred
local_csr_wr[ACTIVE_CTX_FUTURE_COUNT, ME_TIMER_COUNTER_VAL]

// install signal to be used when timestamp is triggered
local_csr_wr[ACTIVE_FUTURE_COUNT_SIGNAL, SIGNAL2]	// signal2 = 2
multi_nop(3)

alu[--, me, -, 0x0]	// if ME0
bne[wait_for_timestamp_signal#]
	cap[fast_wr, 0x180, MISC_CONTROL] // ME0 enables TIMERSTAMP_EN
	multi_nop(3)


wait_for_timestamp_signal#:
// ME0-ME7 waits for timestamp to be triggered
ctx_arb[signal_2]

; Read TIMESTAMP_Low register
local_csr_rd[Timestamp_low]
immed[timer_rd_low,0]	// Timestamp_low = timer_rd_low


// Write status of timer_rd_low into scratch to be checked by XScale
alu[$status0, --, B, timer_rd_low]

scratch[write, $status0, scratch_base, ME_OFFSET, 1], sig_done[scratch_write]
ctx_arb[scratch_write]

end#:
nop
nop
nop
nop
nop
ctx_arb[kill]
nop
nop
nop
nop
nop