pl_media_loopback_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.0.439
+uca_date: Oct  7 2002 00:17:47
+current_date: Thu Nov 28 14:34:18 2002

.cpu_version 0x00000002 0 15

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:cont1# 109
:cont_init1# 13
:cont_init2# 31
:init_rbuf# 37
:init_value# 0
:not_ctx_0# 3
:not_ctx_1# 6
:not_ctx_2# 9
:not_ctx_3# 12
:receivepacket# 72
:rsw# 81
*-- no_destination 0
*$l0000!transferreg00 sram_rel 00 0 both 2 0x4E
*$l0000!transferreg01 sram_rel 01 0 both 1 0x4E
;*l0000!rxthreadlist!!2 gpr_a_rel 0B
;*l0000!rxthreadlist!!3 gpr_b_rel 03
*l0000!rxthreadlist gpr_a_rel 0B
*l0000!bytecnt gpr_a_rel 00
*l0000!elem gpr_a_rel 01
*l0000!error gpr_b_rel 00
*l0000!rx_channel_num gpr_b_rel 01
;*l0000!rxconfigdata!!2 gpr_a_rel 02
*l0000!rxconfigdata gpr_b_rel 0B
*l0000!rbuf gpr_a_rel 03
*l0000!ring_num gpr_a_rel 04
;*l0000!msfaddress!!2 gpr_b_rel 0D
;*l0000!msfaddress!!3 gpr_b_rel 0D
;*l0000!msfaddress!!4 gpr_b_rel 0D
;*l0000!msfaddress!!5 gpr_b_rel 0D
;*l0000!msfaddress!!6 gpr_b_rel 0D
*l0000!msfaddress gpr_b_rel 0D
*l0000!threadfreelist_addr gpr_b_rel 02
*l0000!elementdone_addr gpr_b_rel 03
;*l0000!drampacketbase!!2 gpr_b_rel 04
*l0000!drampacketbase gpr_a_rel 0C
*l0001!temp gpr_b_rel 04
*l0001!cur_me gpr_b_rel 0E
*l0001!cur_ctx gpr_b_rel 0F
*l0002!rxconfigdata0 gpr_b_rel 00
*$l0002!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0003!temp_reg gpr_b_rel 0B
*l0003!temp gpr_b_rel 0C
*l0004!rxupcontrol gpr_b_rel 01
*$l0004!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0005!rxconfigdata0 gpr_b_rel 05
*$l0005!rxconfigdata0 sram_rel 00 0 both 1 0x0
*$l0006!scratch_base sram_rel 00 0 both 1 0x0
*$l0006!scratch_head sram_rel 01 0 both 1 0x0
*$l0006!scratch_tail sram_rel 02 0 both 1 0x0
*l0007!pci_base gpr_a_rel 08
*l0007!pci_offset gpr_b_rel 07
*$l0007!pci_rw sram_rel 00 0 both 1 0x0
*l0008!temp gpr_b_rel 08
*l0008!cur_ctx gpr_a_rel 09
*$l0008!temp_val sram_rel 00 0 both 1 0x0
;*l0008!temp_addr!!2 gpr_b_rel 0A
*l0008!temp_addr gpr_b_rel 0A
*l0009!temp gpr_b_rel 05
*l0009!cur_ctx gpr_a_rel 05
*$l0009!temp_val sram_rel 00 0 both 1 0x0
;*l0009!temp_addr!!2 gpr_b_rel 06
;*l0009!temp_addr!!3 gpr_b_rel 06
;*l0009!temp_addr!!4 gpr_b_rel 06
;*l0009!temp_addr!!5 gpr_b_rel 06
;*l0009!temp_addr!!6 gpr_b_rel 06
;*l0009!temp_addr!!7 gpr_b_rel 06
;*l0009!temp_addr!!8 gpr_b_rel 06
*l0009!temp_addr gpr_b_rel 06
*l0010!rbufoffset gpr_b_rel 07
;*l0010!refcnt!!2 gpr_b_rel 08
*l0010!refcnt gpr_a_rel 06
;*l0010!temp!!2 gpr_b_rel 09
;*l0010!temp!!3 gpr_b_rel 09
*l0010!temp gpr_b_rel 09
*$l0011!temp0 sram_rel 00 0 both 1 0x0
*$l0012!scratch_data sram_rel 00 0 both 1 0x0
*l0012!temp gpr_a_rel 0A
;*l0012!temp_addr!!2 gpr_b_rel 0A
*l0012!temp_addr gpr_a_rel 07
*l0012!scratch_sig signal 01 0
*l0012!scratch_sig!!2 signal 01 0
*l0009!scratch_sig signal 01 0
*l0009!scratch_sig!!4 signal 01 0
*l0009!scratch_sig!!3 signal 01 0
*l0009!scratch_sig!!2 signal 01 0
*l0008!scratch_sig signal 01 0
*l0007!pci_sig signal 01 0
*l0006!scratch_sig3 signal 03 0
*l0006!scratch_sig2 signal 02 0
*l0006!scratch_sig1 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig_thd signal 01 0
*l0000!sig_dram_xfer1 signal 02 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var l0012!temp_addr 0 R
.%liverange 0 A7 118:118
.%liverange 0 B10 119:124
.%liverange 0 ~B10 72:78
.%var l0012!temp 0 R
.%liverange 0 A10 122:124
.%liverange 0 ~A10 72:121
.%var $l0012!scratch_data 0 R
.%liverange 0 $W0 120:124
.%liverange 0 ~$W0 72:77
.%liverange 0 $R0 125:125
.%var $l0011!temp0 0 R
.%liverange 0 $W0 116:119
.%liverange 0 $R0 125:125
.%var l0010!temp 0 R
.%liverange 0 B9 111:124
.%liverange 0 ~B9 72:110
.%var l0010!refcnt 0 R
.%liverange 0 A6 105:107 109:124
.%liverange 0 ~A6 72:104
.%liverange 0 B8 108:108
.%var l0010!rbufoffset 0 R
.%liverange 0 B7 110:124
.%liverange 0 ~B7 72:109
.%var l0009!temp_addr 0 R
.%liverange 0 B6 90:124
.%liverange 0 ~B6 72:89
.%var $l0009!temp_val 0 R
.%liverange 0 $W0 89:115
.%liverange 0 $R0 125:125
.%var l0009!cur_ctx 0 R
.%liverange 0 A5 88:124
.%liverange 0 ~A5 72:87
.%var l0009!temp 0 R
.%liverange 0 B5 87:124
.%liverange 0 ~B5 72:86
.%var l0008!temp_addr 0 R
.%liverange 0 B10 79:118
.%var $l0008!temp_val 0 R
.%liverange 0 $W0 78:88
.%liverange 0 $R0 125:125
.%var l0008!cur_ctx 0 R
.%liverange 0 A9 77:124
.%liverange 0 ~A9 72:76
.%var l0008!temp 0 R
.%liverange 0 B8 76:107
.%liverange 0 ~B8 72:75 109:124
.%var $l0007!pci_rw 0 R
.%liverange 0 $W0 68:71
.%liverange 0 ~$W0 72:77
.%liverange 0 $R0 125:125
.%var l0007!pci_offset 0 R
.%liverange 0 B7 67:71
.%liverange 0 ~B7 72:109
.%var l0007!pci_base 0 R
.%liverange 0 A8 65:71
.%liverange 0 ~A8 72:124
.%var $l0006!scratch_tail 0 R
.%liverange 0 $W2 59:71
.%liverange 0 ~$W2 72:124
.%liverange 0 $R2 125:125
.%var $l0006!scratch_head 0 R
.%liverange 0 $W1 58:71
.%liverange 0 ~$W1 72:124
.%liverange 0 $R1 125:125
.%var $l0006!scratch_base 0 R
.%liverange 0 $W0 60:67
.%liverange 0 $R0 125:125
.%var $l0005!rxconfigdata0 0 R
.%liverange 0 $W0 55:59
.%liverange 0 $R0 125:125
.%var l0005!rxconfigdata0 0 R
.%liverange 0 B5 53:71
.%liverange 0 ~B5 72:86
.%var $l0004!rxconfigdata0 0 R
.%liverange 0 $W0 44:54
.%liverange 0 $R0 125:125
.%var l0004!rxupcontrol 0 R
.%liverange 0 B1 43:71
.%liverange 0 ~B1 72:84
.%var l0003!temp 0 R
.%liverange 0 B12 38:71
.%liverange 0 ~B12 37:37 72:124
.%var l0003!temp_reg 0 R
.%liverange 0 B11 37:71
.%liverange 0 ~B11 72:124
.%var $l0002!rxconfigdata0 0 R
.%liverange 0 $W0 34:43
.%liverange 0 $R0 125:125
.%var l0002!rxconfigdata0 0 R
.%liverange 0 B0 32:71
.%liverange 0 ~B0 72:83
.%var l0001!cur_ctx 0 R
.%liverange 0 B15 17:124
.%var l0001!cur_me 0 R
.%liverange 0 B14 16:124
.%var l0001!temp 0 R
.%liverange 0 B4 15:19
.%var l0000!drampacketbase 0 R
.%liverange 0 A12 18:19
.%liverange 0 B4 20:124
.%var l0000!elementdone_addr 0 R
.%liverange 0 B3 26:124
.%var l0000!threadfreelist_addr 0 R
.%liverange 0 B2 2:2 5:5 8:8 11:11 13:124
.%var l0000!msfaddress 0 R
.%liverange 0 B13 35:71
.%liverange 0 ~B13 72:124
.%var l0000!ring_num 0 R
.%liverange 0 A4 28:124
.%var l0000!rbuf 0 R
.%liverange 0 A3 27:124
.%var l0000!rxconfigdata 0 R
.%liverange 0 B11 24:24
.%liverange 0 A2 25:124
.%var l0000!rx_channel_num 0 R
.%liverange 0 B1 85:124
.%liverange 0 ~B1 72:84
.%var l0000!error 0 R
.%liverange 0 B0 84:124
.%liverange 0 ~B0 72:83
.%var l0000!elem 0 R
.%liverange 0 A1 82:124
.%liverange 0 ~A1 72:81
.%var l0000!bytecnt 0 R
.%liverange 0 A0 83:124
.%liverange 0 ~A0 72:82
.%var l0000!rxthreadlist 0 R
.%liverange 0 A11 21:22
.%liverange 0 B3 23:25
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 125:125
.%liverange 0 $R1 125:125
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:33
.%liverange 0 ~$W0 72:77
.%liverange 0 $R0 0:124
.%var l0012!scratch_sig 1 R
.%liverange 0 G1 121:121
.%liverange 0 G1 124:124
.%var l0009!scratch_sig 1 R
.%liverange 0 G1 92:92 96:96 100:100 104:104
.%var l0008!scratch_sig 1 R
.%liverange 0 G1 81:81
.%var l0007!pci_sig 1 R
.%liverange 0 G1 69:69
.%var l0006!scratch_sig3 1 R
.%liverange 0 G3 63:64
.%var l0006!scratch_sig2 1 R
.%liverange 0 G2 62:64
.%var l0006!scratch_sig1 1 R