sys_loopback_bd_3_eg_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:02:08 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:0xfbfb# 98
:check_ring_full# 95
:init_rbuf# 45
:init_thread0_only# 21
:l000_01# 86
:l000_end# 87
:l001_01# 97
:l001_end# 97
:next_packet# 97
:null# 97
:receivenextpacket# 65
:rsw# 68
*-- no_destination 0
*l0000!cur_me gpr_b_rel 00
*l0000!cur_ctx gpr_a_rel 00
*l0000!sram_channel_number gpr_b_rel 0B
*l0000!t0 gpr_b_rel 0C
*@l0000!total_rx gpr_a_abs 01
*@l0000!total_packet gpr_b_abs 01
*@l0000!total_rx_cnt gpr_b_abs 11
*@l0000!cur_loop gpr_b_abs 21
*@l0000!total_loop gpr_b_abs 31
*l0000!ring gpr_b_rel 02
;*l0000!rxconfigdata!!2 gpr_a_rel 05
*l0000!rxconfigdata gpr_b_rel 0D
*l0000!rbuf_base gpr_a_rel 02
*l0000!rbuf_elem_done gpr_b_rel 0E
*l0000!rx_thd_freelist gpr_b_rel 03
*l0000!null gpr_b_rel 0F
*l0000!elem gpr_b_rel 04
*$l0000!sequence_count sram_rel 01 0 both 1 0x0
*$l0000!ring_data sram_rel 00 0 both 1 0x0
*$l0000!pkt_number sram_rel 00 0 both 1 0x0
*@l0000!sramdescbase gpr_b_abs 41
*@l0000!drampacketbase gpr_b_abs 51
*@l0000!expected_sequence_0 gpr_a_abs 11
*$l0000!transferreg00 sram_rel 00 0 both 2 0x2D
*$l0000!transferreg01 sram_rel 01 0 both 1 0x2D
*l0001!temp_data gpr_b_rel 02
;*l0002!rxthreadlist!!2 gpr_b_rel 00
;*l0002!rxthreadlist!!3 gpr_b_rel 00
*l0002!rxthreadlist gpr_a_rel 03
*l0002!temp_data gpr_a_rel 04
;*l0002!me_data!!2 gpr_b_rel 05
*l0002!me_data gpr_b_rel 05
*l0003!temp_scratch_addr gpr_b_rel 04
*$l0003!temp_scratch_data sram_rel 01 0 both 1 0x0
*l0003!temp_data gpr_b_rel 06
*l0004!temp_scratch_addr gpr_b_rel 07
*$l0004!temp_scratch_data sram_rel 01 0 both 1 0x0
*l0005!msfaddress gpr_b_rel 08
*l0005!rxcontroldata gpr_b_rel 09
*$l0005!rxcontroldata sram_rel 00 0 both 1 0x0
*l0006!msfaddress gpr_b_rel 0A
*$l0006!csixtypemapdata sram_rel 00 0 both 1 0x0
*l0007!temp_reg gpr_b_rel 06
*l0007!rbufelemdonedata gpr_b_rel 07
*l0008!msfaddress gpr_b_rel 0B
*$l0008!rxcontroldata sram_rel 01 0 both 1 0x0
;*l0009!timeout_val!!2 gpr_b_rel 0C
*l0009!timeout_val gpr_b_rel 0C
*$l0010!scratch_base sram_rel 00 0 both 1 0x0
*$l0010!scratch_head sram_rel 01 0 both 1 0x0
*$l0010!scratch_tail sram_rel 02 0 both 1 0x0
*l0010!temp_val gpr_b_rel 0D
*l0011!temp_scratch_addr gpr_b_rel 0E
*l0012!ind_ref_data gpr_b_rel 08
*l0013!rbufaddress gpr_b_rel 09
*l0014!temp_sequence gpr_b_rel 0A
*l0015!rbuf_elem_done_data gpr_b_rel 0F
*$l0016!temp_scratch sram_rel 00 0 both 1 0x0
*l0016!temp_scratch_addr gpr_b_rel 03
*l0010!scratch_sig3 signal 03 0
*l0010!scratch_sig2 signal 02 0
*l0010!scratch_sig1 signal 01 0
*l0004!scratch_sig signal 01 0
*l0003!scratch_sig signal 01 0
*l0000!scratch_rx signal 02 0
*l0000!ring_sig signal 01 0
*l0000!scratch_sig signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!next_ctx_sig signal 0E 0
*l0000!rx_sig signal 01 0
.%type R
.%type SI
.%scope global
.%var l0016!temp_scratch_addr 0 R
.%liverange 0 B3 100:101
.%var $l0016!temp_scratch 0 R
.%liverange 0 $W0 99:101
.%liverange 0 $R0 102:102
.%var l0015!rbuf_elem_done_data 0 R
.%liverange 0 B15 88:96
.%liverange 0 ~B15 65:68 97:97
.%var l0014!temp_sequence 0 R
.%liverange 0 B10 81:96 98:101
.%liverange 0 ~B10 65:80 97:97
.%var l0013!rbufaddress 0 R
.%liverange 0 B9 77:96 98:101
.%liverange 0 ~B9 65:76 97:97
.%var l0012!ind_ref_data 0 R
.%liverange 0 B8 79:96 98:101
.%liverange 0 ~B8 65:78 97:97
.%var l0011!temp_scratch_addr 0 R
.%liverange 0 B14 73:96 98:101
.%liverange 0 ~B14 65:72 97:97
.%var l0010!temp_val 0 R
.%liverange 0 B13 58:64
.%liverange 0 ~B13 65:101
.%var $l0010!scratch_tail 0 R
.%liverange 0 $W2 61:64
.%liverange 0 ~$W2 65:101
.%liverange 0 $R2 102:102
.%var $l0010!scratch_head 0 R
.%liverange 0 $W1 60:64
.%liverange 0 ~$W1 65:101
.%liverange 0 $R1 102:102
.%var $l0010!scratch_base 0 R
.%liverange 0 $W0 59:64
.%liverange 0 ~$W0 65:71 97:97
.%liverange 0 $R0 102:102
.%var l0009!timeout_val 0 R
.%liverange 0 B12 55:64
.%liverange 0 ~B12 65:101
.%var $l0008!rxcontroldata 0 R
.%liverange 0 $W1 53:59
.%liverange 0 $R1 52:64
.%liverange 0 ~$R1 65:77 97:97
.%var l0008!msfaddress 0 R
.%liverange 0 B11 51:64
.%liverange 0 ~B11 65:101
.%var l0007!rbufelemdonedata 0 R
.%liverange 0 B7 46:64
.%liverange 0 ~B7 45:45 65:101
.%var l0007!temp_reg 0 R
.%liverange 0 B6 45:64
.%liverange 0 ~B6 65:101
.%var $l0006!csixtypemapdata 0 R
.%liverange 0 $W0 42:58
.%liverange 0 $R0 102:102
.%var l0006!msfaddress 0 R
.%liverange 0 B10 43:64
.%liverange 0 ~B10 65:80 97:97
.%var $l0005!rxcontroldata 0 R
.%liverange 0 $W0 39:41
.%liverange 0 $R0 102:102
.%var l0005!rxcontroldata 0 R
.%liverange 0 B9 37:64
.%liverange 0 ~B9 65:76 97:97
.%var l0005!msfaddress 0 R
.%liverange 0 B8 40:64
.%liverange 0 ~B8 65:78 97:97
.%var $l0004!temp_scratch_data 0 R
.%liverange 0 $W1 102:102
.%liverange 0 $R1 35:51
.%var l0004!temp_scratch_addr 0 R
.%liverange 0 B7 34:44
.%liverange 0 ~B7 45:45
.%var l0003!temp_data 0 R
.%liverange 0 B6 32:44
.%var $l0003!temp_scratch_data 0 R
.%liverange 0 $W1 102:102
.%liverange 0 $R1 31:34
.%var l0003!temp_scratch_addr 0 R
.%liverange 0 B4 30:64
.%liverange 0 ~B4 65:74 97:97
.%var l0002!me_data 0 R
.%liverange 0 B5 11:101
.%var l0002!temp_data 0 R
.%liverange 0 A4 12:101
.%var l0002!rxthreadlist 0 R
.%liverange 0 A3 14:14
.%liverange 0 B0 15:101
.%var l0001!temp_data 0 R
.%liverange 0 B2 2:4
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 102:102
.%liverange 0 $R1 102:102
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:38
.%liverange 0 ~$W0 65:71 97:97
.%liverange 0 $R0 0:101
.%var @l0000!expected_sequence_0 0 R
.%liverange 0 @A17 0:101
.%var @l0000!drampacketbase 0 R
.%liverange 0 @B81 0:101
.%var @l0000!sramdescbase 0 R
.%liverange 0 @B65 0:101
.%var $l0000!pkt_number 0 R
.%liverange 0 $W0 72:94 98:98
.%liverange 0 ~$W0 65:71 97:97
.%liverange 0 $R0 102:102
.%var $l0000!ring_data 0 R
.%liverange 0 $W0 95:96
.%liverange 0 ~$W0 65:71 97:97
.%liverange 0 $R0 102:102
.%var $l0000!sequence_count 0 R
.%liverange 0 $W1 102:102
.%liverange 0 $R1 78:96 98:101
.%liverange 0 ~$R1 65:77 97:97
.%var l0000!elem 0 R
.%liverange 0 B4 75:96 98:101
.%liverange 0 ~B4 65:74 97:97
.%var l0000!null 0 R
.%liverange 0 B15 69:87 98:101
.%liverange 0 ~B15 65:68 97:97
.%var l0000!rx_thd_freelist 0 R
.%liverange 0 B3 10:99
.%var l0000!rbuf_elem_done 0 R
.%liverange 0 B14 9:64
.%liverange 0 ~B14 65:72 97:97
.%var l0000!rbuf_base 0 R
.%liverange 0 A2 8:101
.%var l0000!rxconfigdata 0 R
.%liverange 0 B13 17:17
.%liverange 0 A5 18:101
.%var l0000!ring 0 R
.%liverange 0 B2 5:101
.%var @l0000!total_loop 0 R
.%liverange 0 @B49 0:101
.%var @l0000!cur_loop 0 R
.%liverange 0 @B33 0:101
.%var @l0000!total_rx_cnt 0 R
.%liverange 0 @B17 0:101
.%var @l0000!total_packet 0 R
.%liverange 0 @B1 0:101
.%var @l0000!total_rx 0 R
.%liverange 0 @A1 0:101
.%var l0000!t0 0 R
.%liverange 0 B12 7:54
.%liverange 0 ~B12 65:101
.%var l0000!sram_channel_number 0 R
.%liverange 0 B11 6:50
.%liverange 0 ~B11 65:101
.%var l0000!cur_ctx 0 R
.%liverange 0 A0 4:101
.%var l0000!cur_me 0 R
.%liverange 0 B0 3:14
.%var l0010!scratch_sig3 1 R