sys_loopback_bd_3_in_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:02:08 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:3# 83
:addfreelist# 32
:cont1# 98
:context_enable_csr_config# 14
:fill# 106
:here# 0
:init_common# 65
:init_rbuf# 38
:init_value# 7
:initstart# 58
:next_packet# 111
:null# 111
:receivepacket# 72
:rsw# 75
:scratch_write# 104
:start# 58
*-- no_destination 0
*$l0000!transferreg00 sram_rel 01 0 both 2 0x50
*$l0000!transferreg01 sram_rel 02 0 both 1 0x50
*l0000!channel_number gpr_b_rel 03
;*l0000!temp!!2 gpr_b_rel 02
;*l0000!temp!!3 gpr_b_rel 02
;*l0000!temp!!4 gpr_b_rel 02
;*l0000!temp!!5 gpr_b_rel 02
;*l0000!temp!!6 gpr_a_rel 00
;*l0000!temp!!7 gpr_b_rel 02
;*l0000!temp!!8 gpr_b_rel 02
*l0000!temp gpr_b_rel 02
*l0000!t0 gpr_b_rel 03
*$l0000!temp0 sram_rel 00 0 both 2 0x42
*$l0000!temp1 sram_rel 01 0 both 1 0x42
;*l0000!rxthreadlist!!2 gpr_a_rel 06
;*l0000!rxthreadlist!!3 gpr_b_rel 08
*l0000!rxthreadlist gpr_a_rel 06
*l0000!sopbit gpr_b_rel 0B
*l0000!eopbit gpr_b_rel 0C
*l0000!bytecnt gpr_a_rel 01
*l0000!elem gpr_a_rel 02
;*l0000!rxconfigdata!!2 gpr_a_rel 03
*l0000!rxconfigdata gpr_b_rel 0D
*$l0000!rxconfigdata0 sram_rel 00 0 both 1 0x0
;*l0000!rxconfigdata0!!2 gpr_b_rel 0C
*l0000!rxconfigdata0 gpr_b_rel 0C
*l0000!null gpr_b_rel 0E
*l0000!rbuf gpr_a_rel 04
*l0000!ring gpr_b_rel 04
*l0000!bdptr gpr_b_rel 0F
;*l0000!msfaddress!!2 gpr_b_rel 0D
*l0000!msfaddress gpr_b_rel 0D
*l0000!msfaddress0 gpr_b_rel 05
*l0000!msfaddress1 gpr_b_rel 09
*l0000!msfaddress2 gpr_b_rel 0E
*@l0000!sramdescbase gpr_a_abs 05
*@l0000!drampacketbase gpr_a_abs 15
*l0000!mask_qa gpr_b_rel 04
*l0000!error gpr_b_rel 01
*l0000!got_pkt gpr_b_rel 03
*$l0000!sr0 sram_rel 00 0 both 4 0x1F
*$l0000!sr1 sram_rel 01 0 both 3 0x1F
*$l0000!sr2 sram_rel 02 0 both 2 0x1F
*$l0000!sr3 sram_rel 03 0 both 1 0x1F
*l0000!rxupcontrol0 gpr_b_rel 0F
*@l0000!counter gpr_a_abs 25
*@l0000!total_rx gpr_a_abs 35
*l0001!cellcount gpr_b_rel 05
*l0001!freelist gpr_b_rel 06
*$l0001!s0 sram_rel 00 0 both 3 0x14
*$l0001!s1 sram_rel 01 0 both 2 0x14
*$l0001!s2 sram_rel 02 0 both 1 0x14
;*l0001!tmp!!2 gpr_b_rel 00
;*l0001!tmp!!3 gpr_b_rel 00
;*l0001!tmp!!4 gpr_a_rel 07
*l0001!tmp gpr_b_rel 00
*l0002!temp_reg gpr_b_rel 07
*l0003!ctxenabledata gpr_b_rel 01
*l0004!cur_me gpr_b_rel 08
*l0004!cur_ctx gpr_b_rel 09
*l0005!temp_scratch_addr gpr_b_rel 0B
*$l0005!pkt_number sram_rel 00 0 both 1 0x0
*l0006!pkt_buff_addr gpr_b_rel 06
;*l0006!rel!!2 gpr_b_rel 0A
*l0006!rel gpr_b_rel 0A
*l0006!rbufoffset gpr_b_rel 07
;*l0006!refcnt!!2 gpr_b_rel 00
*l0006!refcnt gpr_b_rel 00
*l0006!freebuffer gpr_b_rel 01
*l0001!qa_init signal 01 0
*l0001!qa_init!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig_thd signal 01 0
*l0000!next_ctx_sig signal 04 0
*l0000!sig_free_buf signal 01 0
*l0000!sig_dram_xfer1 signal 02 0
*l0000!scratch_sig signal 01 0
*l0000!scratch_sig!!2 signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var l0006!freebuffer 0 R
.%liverange 0 B1 91:110
.%liverange 0 ~B1 72:81 111:111
.%var l0006!refcnt 0 R
.%liverange 0 B0 95:110
.%liverange 0 ~B0 72:94 111:111
.%var l0006!rbufoffset 0 R
.%liverange 0 B7 100:110
.%liverange 0 ~B7 72:99 111:111
.%var l0006!rel 0 R
.%liverange 0 B10 92:110
.%liverange 0 ~B10 72:91 111:111
.%var l0006!pkt_buff_addr 0 R
.%liverange 0 B6 94:110
.%liverange 0 ~B6 72:93 111:111
.%var $l0005!pkt_number 0 R
.%liverange 0 $W0 87:105
.%liverange 0 $R0 112:112
.%var l0005!temp_scratch_addr 0 R
.%liverange 0 B11 88:110
.%liverange 0 ~B11 72:79 111:111
.%var l0004!cur_ctx 0 R
.%liverange 0 B9 62:67
.%var l0004!cur_me 0 R
.%liverange 0 B8 61:64
.%var l0003!ctxenabledata 0 R
.%liverange 0 B1 56:57
.%liverange 0 ~B1 58:81 111:111
.%var l0002!temp_reg 0 R
.%liverange 0 B7 38:57
.%liverange 0 ~B7 58:99 111:111
.%var l0001!tmp 0 R
.%liverange 0 B0 20:26
.%liverange 0 A7 27:57
.%liverange 0 ~A7 58:111
.%var $l0001!s2 0 R
.%liverange 0 $W2 24:57
.%liverange 0 ~$W2 58:111
.%liverange 0 $R2 112:112
.%var $l0001!s1 0 R
.%liverange 0 $W1 23:57
.%liverange 0 ~$W1 58:111
.%liverange 0 $R1 112:112
.%var $l0001!s0 0 R
.%liverange 0 $W0 22:44
.%liverange 0 $R0 112:112
.%var l0001!freelist 0 R
.%liverange 0 B6 30:57
.%liverange 0 ~B6 58:93 111:111
.%var l0001!cellcount 0 R
.%liverange 0 B5 32:57
.%liverange 0 ~B5 58:66
.%var @l0000!total_rx 0 R
.%liverange 0 @A53 0:111
.%var @l0000!counter 0 R
.%liverange 0 @A37 0:111
.%var l0000!rxupcontrol0 0 R
.%liverange 0 B15 44:57
.%liverange 0 ~B15 58:104 111:111
.%var $l0000!sr3 0 R
.%liverange 0 $W3 112:112
.%liverange 0 $R3 112:112
.%var $l0000!sr2 0 R
.%liverange 0 $W2 112:112
.%liverange 0 $R2 112:112
.%var $l0000!sr1 0 R
.%liverange 0 $W1 112:112
.%liverange 0 $R1 112:112
.%var $l0000!sr0 0 R
.%liverange 0 $W0 112:112
.%liverange 0 $R0 28:57 84:110
.%liverange 0 ~$R0 58:83 111:111
.%var l0000!got_pkt 0 R
.%liverange 0 B3 1:3
.%var l0000!error 0 R
.%liverange 0 B1 82:90
.%var l0000!mask_qa 0 R
.%liverange 0 B4 2:6
.%var @l0000!drampacketbase 0 R
.%liverange 0 @A21 0:111
.%var @l0000!sramdescbase 0 R
.%liverange 0 @A5 0:111
.%var l0000!msfaddress2 0 R
.%liverange 0 B14 46:57
.%liverange 0 ~B14 58:75
.%var l0000!msfaddress1 0 R
.%liverange 0 B9 68:111
.%var l0000!msfaddress0 0 R
.%liverange 0 B5 67:111
.%var l0000!msfaddress 0 R
.%liverange 0 B13 18:57
.%liverange 0 ~B13 58:68
.%var l0000!bdptr 0 R
.%liverange 0 B15 105:110
.%liverange 0 ~B15 72:104 111:111
.%var l0000!ring 0 R
.%liverange 0 B4 7:111
.%var l0000!rbuf 0 R
.%liverange 0 A4 66:111
.%var l0000!null 0 R
.%liverange 0 B14 76:111
.%liverange 0 ~B14 72:75
.%var l0000!rxconfigdata0 0 R
.%liverange 0 B12 15:57
.%liverange 0 ~B12 58:80 111:111
.%var $l0000!rxconfigdata0 0 R
.%liverange 0 $W0 17:21 45:57
.%liverange 0 ~$W0 58:86 111:111
.%liverange 0 $R0 112:112
.%var l0000!rxconfigdata 0 R
.%liverange 0 B13 69:69
.%liverange 0 A3 70:111
.%var l0000!elem 0 R
.%liverange 0 A2 79:110
.%liverange 0 ~A2 72:78 111:111
.%var l0000!bytecnt 0 R
.%liverange 0 A1 83:110
.%liverange 0 ~A1 72:82 111:111
.%var l0000!eopbit 0 R
.%liverange 0 B12 81:110
.%liverange 0 ~B12 72:80 111:111
.%var l0000!sopbit 0 R
.%liverange 0 B11 80:87
.%var l0000!rxthreadlist 0 R
.%liverange 0 A6 63:64
.%liverange 0 B8 65:111
.%var $l0000!temp1 0 R
.%liverange 0 $W1 112:112
.%liverange 0 $R1 112:112
.%var $l0000!temp0 0 R
.%liverange 0 $W0 106:110
.%liverange 0 ~$W0 72:86 111:111
.%liverange 0 $R0 112:112
.%var l0000!t0 0 R
.%liverange 0 B3 5:111
.%var l0000!temp 0 R
.%liverange 0 B2 39:57 60:101 103:111