sys_loopback_bd_3_eg_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:02:08 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:init# 2
:init_msf# 16
:l000_01# 68
:l000_end# 69
:l001_01# 60
:l001_end# 60
:msf_init_done# 30
:next_burst# 31
:next_packet# 39
:wait_for_xscale# 63
*-- no_destination 0
;*l0000!msfaddress!!2 gpr_b_rel 03
;*l0000!msfaddress!!3 gpr_b_rel 03
;*l0000!msfaddress!!4 gpr_a_rel 04
;*l0000!msfaddress!!5 gpr_a_rel 04
*l0000!msfaddress gpr_b_rel 03
*l0000!txsequenceaddr gpr_b_rel 0B
*l0000!pkt_in_one_burst gpr_a_rel 00
*l0000!pkt_in_cur_burst gpr_b_rel 04
*l0000!total_loop gpr_a_rel 01
*l0000!cur_loop gpr_b_rel 00
;*l0000!future_count_value!!2 gpr_b_rel 05
*l0000!future_count_value gpr_a_rel 02
;*l0000!future_count_incr!!2 gpr_b_rel 01
*l0000!future_count_incr gpr_b_rel 01
*l0000!byte_count gpr_a_rel 03
*$l0000!misc_ctrl_val sram_rel 00 0 both 1 0x0
;*l0000!txconfigdata0!!2 gpr_b_rel 06
;*l0000!txconfigdata0!!3 gpr_b_rel 06
*l0000!txconfigdata0 gpr_b_rel 06
*$l0000!txconfigdata0 sram_rel 00 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x13
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x13
;*l0000!tbuf_element!!2 gpr_b_rel 02
*l0000!tbuf_element gpr_b_rel 02
*l0001!temp_scratch_addr gpr_b_rel 0C
*$l0001!temp_scratch_data sram_rel 00 0 both 1 0x0
*l0002!temp_scratch_addr gpr_b_rel 08
*$l0002!temp_scratch_data sram_rel 00 0 both 1 0x0
*l0003!temp_scratch_addr gpr_b_rel 09
*$l0003!temp_scratch_data sram_rel 00 0 both 1 0x0
*l0004!temp gpr_b_rel 07
*$l0005!temp_reg_val sram_rel 02 0 both 1 0x0
*l0005!temp_scratch_addr gpr_b_rel 0A
*$l0005!temp_scratch_data sram_rel 01 0 both 1 0x0
*l0005!scratch_sig signal 02 0
*l0003!scratch_sig signal 01 0
*l0002!scratch_sig signal 01 0
*l0001!scratch_sig signal 01 0
*l0000!cap_sig signal 02 0
*l0000!cap_sig!!2 signal 02 0
*l0000!inter_me_sig signal 0F 0
*l0000!future_count_sig signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var $l0005!temp_scratch_data 0 R
.%liverange 0 $W1 63:67
.%liverange 0 ~$W1 31:47
.%liverange 0 $R1 64:67
.%liverange 0 ~$R1 31:63 68:69
.%var l0005!temp_scratch_addr 0 R
.%liverange 0 B10 62:67
.%liverange 0 ~B10 31:61 68:69
.%var $l0005!temp_reg_val 0 R
.%liverange 0 $W2 56:67
.%liverange 0 ~$W2 31:55 68:69
.%liverange 0 $R2 70:70
.%var l0004!temp 0 R
.%liverange 0 B7 46:69
.%liverange 0 ~B7 31:45
.%var $l0003!temp_scratch_data 0 R
.%liverange 0 $W0 70:70
.%liverange 0 $R0 15:30
.%var l0003!temp_scratch_addr 0 R
.%liverange 0 B9 14:69
.%var $l0002!temp_scratch_data 0 R
.%liverange 0 $W0 70:70
.%liverange 0 $R0 12:14
.%var l0002!temp_scratch_addr 0 R
.%liverange 0 B8 11:69
.%var $l0001!temp_scratch_data 0 R
.%liverange 0 $W0 70:70
.%liverange 0 $R0 9:11
.%var l0001!temp_scratch_addr 0 R
.%liverange 0 B12 8:69
.%var l0000!tbuf_element 0 R
.%liverange 0 B2 3:69
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 48:62 68:69
.%liverange 0 ~$W1 39:47
.%liverange 0 $R1 70:70
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 47:69
.%liverange 0 ~$W0 31:46
.%liverange 0 $R0 70:70
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W0 20:30
.%liverange 0 ~$W0 31:46
.%liverange 0 $R0 70:70
.%var l0000!txconfigdata0 0 R
.%liverange 0 B6 18:69
.%var $l0000!misc_ctrl_val 0 R
.%liverange 0 $W0 70:70
.%liverange 0 $R0 31:69
.%var l0000!byte_count 0 R
.%liverange 0 A3 4:69
.%var l0000!future_count_incr 0 R
.%liverange 0 B1 6:69
.%var l0000!future_count_value 0 R
.%liverange 0 A2 33:40 42:69
.%liverange 0 ~A2 31:32
.%liverange 0 B5 41:41
.%var l0000!cur_loop 0 R
.%liverange 0 B0 5:69
.%var l0000!total_loop 0 R
.%liverange 0 A1 13:69
.%var l0000!pkt_in_cur_burst 0 R
.%liverange 0 B4 32:69
.%liverange 0 ~B4 31:31
.%var l0000!pkt_in_one_burst 0 R
.%liverange 0 A0 16:69
.%var l0000!txsequenceaddr 0 R
.%liverange 0 B11 7:69
.%var l0000!msfaddress 0 R
.%liverange 0 B3 17:30
.%liverange 0 ~B3 31:43
.%liverange 0 A4 44:69
.%liverange 0 ~A4 31:43
.%var l0005!scratch_sig 1 R
.%liverange 0 D2 64:65
.%var l0003!scratch_sig 1 R
.%liverange 0 G1 15:15
.%var l0002!scratch_sig 1 R
.%liverange 0 G1 12:12
.%var l0001!scratch_sig 1 R
.%liverange 0 G1 9:9
.%var l0000!cap_sig 1 R
.%liverange 0 G2 31:31 57:61
.%var l0000!inter_me_sig 1 R
.%liverange 0 G15 70:70
.%var l0000!future_count_sig 1 R
.%liverange 0 G1 43:49
.%var l0000!msf_sig 1 R
.%liverange 0 G1 21:21 25:25 30:30 50:61 68:69
.%scope end
.0 D800800010 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 63 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg l0000!msfaddress l0000!txsequenceaddr
	.%line 64 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg l0000!pkt_in_one_burst l0000!pkt_in_cur_burst
	.%line 65 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg l0000!total_loop l0000!cur_loop
	.%line 66 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg l0000!future_count_value l0000!future_count_incr
	.%line 67 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg l0000!byte_count
	.%line 68 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg $l0000!misc_ctrl_val
	.%line 69 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg l0000!txconfigdata0
	.%line 70 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg $l0000!txconfigdata0
	.%line 71 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 72 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.reg l0000!tbuf_element l0000!base_element_for_port
	.%line 73 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.sig l0000!msf_sig l0000!future_count_sig l0000!inter_me_sig l0000!cap_sig
	.%line 75 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.xfer_order $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 77 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.addr l0000!inter_me_sig 15
	.%line 79 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.set_sig l0000!inter_me_sig
	.%line 80 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0 2
	br=ctx[0, init#]
.1 E000010000 common_code
	.%line 81 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	ctx_arb[kill], any
.2 F000000B00 common_code
	.%line 83 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	init#:
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		immed[l0000!tbuf_element, 0]
.3 F0000CC003 common_code
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		immed[l0000!byte_count, 48]
.4 F000000300 common_code
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		immed[l0000!cur_loop, 0]
.5 F000000723 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		immed[l0000!future_count_incr, 35]
.6 F000002F60 common_code
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		immed[l0000!txsequenceaddr, 0x0060]
.7 F001603300 common_code
	.%line 91 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.begin
	.%line 92 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		.reg l0001!temp_scratch_addr $l0001!temp_scratch_data
	.%line 93 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		.sig l0001!scratch_sig
	.%line 94 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		immed[l0001!temp_scratch_addr, 0x1600]
.8 1010003020 common_code
	.%line 95 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		scratch[read, $l0001!temp_scratch_data, 0, l0001!temp_scratch_addr, 1], ctx_swap[l0001!scratch_sig]
.9 B000160000 common_code
	.%line 96 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		alu[l0000!future_count_incr, --, b, $l0001!temp_scratch_data]
.10 F001602304 common_code
	.%line 97 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.end
	.%line 99 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
	.begin
	.%line 100 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		.reg l0002!temp_scratch_addr $l0002!temp_scratch_data
	.%line 101 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		.sig l0002!scratch_sig
	.%line 102 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		immed[l0002!temp_scratch_addr, 0x1604]
.11 1010002020 common_code
	.%line 103 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bd_3\sys_loopback_bd_3_eg_tx.uc" 1 0
		scratch[read, $l0002!temp_scratch_data, 0, l0002!temp_scratch_addr, 1], ctx_swap[l0002!scratch_sig]
.12 A000160000 common_code